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AHgh+Rr1+OT/nA+wzvP2yFncninwoiBY2wCT7doD5dWhaxo1Ox1qsIKzyztRJFD7aAMRQWUgIP5Z/DFWWRlEevs=@vger.kernel.org X-Gm-Message-State: AOJu0YyA8mOBd59c4RWelDICre0Ujf1V2TlirVgufTreCpkspdfR6MpB jp5/y1CKYdf5m2O6uf77IeyyoemUP3kqM7rHj34Be/TsAlURacnmLB495DQhcKY/4PLmHFoWn70 P0tlD4A== X-Received: from pgt36.prod.google.com ([2002:a63:1364:0:b0:c8f:d0d0:d863]) (user=ctshao job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:330b:b0:3bf:6c08:fba4 with SMTP id adf61e73a8af0-3c357637bc4mr4783765637.56.1784061655586; Tue, 14 Jul 2026 13:40:55 -0700 (PDT) Date: Tue, 14 Jul 2026 13:40:41 -0700 In-Reply-To: <20260714204044.1952031-1-ctshao@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260714204044.1952031-1-ctshao@google.com> X-Mailer: git-send-email 2.55.0.141.g00534a21ce-goog Message-ID: <20260714204044.1952031-11-ctshao@google.com> Subject: [PATCH v2 10/12] perf vendor events intel: Update pantherlake events from 1.06 to 1.07 From: Chun-Tse Shao To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org Cc: alexander.shishkin@linux.intel.com, jolsa@kernel.org, adrian.hunter@intel.com, james.clark@linaro.org, afaerber@suse.de, mani@kernel.org, dapeng1.mi@linux.intel.com, thomas.falcon@intel.com, irogers@google.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Chun-Tse Shao Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable The updated events were published in: https://github.com/intel/perfmon/commit/ce70546e9ccca4181d142057171c5bd820c= 8756d Signed-off-by: Chun-Tse Shao --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 7bbb8b237b35..3fffca669710 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -26,7 +26,7 @@ GenuineIntel-6-BD,v1.26,lunarlake,core GenuineIntel-6-(AA|AC|B5),v1.22,meteorlake,core GenuineIntel-6-1[AEF],v4,nehalemep,core GenuineIntel-6-2E,v4,nehalemex,core -GenuineIntel-6-(CC|D5),v1.06,pantherlake,core +GenuineIntel-6-(CC|D5|E5),v1.07,pantherlake,core GenuineIntel-6-A7,v1.04,rocketlake,core GenuineIntel-6-2A,v19,sandybridge,core GenuineIntel-6-8F,v1.39,sapphirerapids,core diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json b/too= ls/perf/pmu-events/arch/x86/pantherlake/pipeline.json index 5d5303c02954..74209da5bc27 100644 --- a/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json @@ -1334,7 +1334,7 @@ "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xc0", "EventName": "INST_RETIRED.REP_ITERATION", - "PublicDescription": "Number of iterations of Repeat (REP) string = retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, a= nd doubleword version and string instructions can be repeated using a repet= ition prefix, REP, that allows their architectural execution to be repeated= a number of times as specified by the RCX register. Note the number of ite= rations is implementation-dependent. Available PDIST counters: 0,1", + "PublicDescription": "Number of iterations of Repeat (REP) string = retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, a= nd doubleword version and string instructions can be repeated using a repet= ition prefix, REP, that allows their architectural execution to be repeated= a number of times as specified by the RCX register. Note: Since the number= of iterations within a REP instruction can be significantly affected by fa= st strings, this event may vary run to run and not match the architectural = number of iterations (specified by RCX) Available PDIST counters: 0,1", "SampleAfterValue": "2000003", "UMask": "0x8", "Unit": "cpu_core" --=20 2.55.0.141.g00534a21ce-goog