From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A04A37CD2C for ; Wed, 15 Jul 2026 14:10:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784124655; cv=none; b=Vzwx2bScYQGhh6XaArT24oYM2BpKCDkV5Dxg/V3UWniBml6M+gisPcifqM/VceW+XmDn2/mIdMol+SN9VsfNWd6hubI+NP8vy0O90YfnWZ7NVBYSVnvwzYBsqrdaIXH3363ehFb/EwSo6+aY/9SlGrOGocBAtOLRzqLKllaZ6i0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784124655; c=relaxed/simple; bh=baQ90teJi7Apuw1DT4Yon0BjJAdFT+yLP4AlGLp6bYg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NTm2UDtwJodnn6yn19z0H1HR8/M51fWaVqfkjS1RzEiU0Ih3a070IiXLEQpC1R/hnvyaJ+sR0NXiS0qKxMT4KmN0BPZs3+8mUxPbzbNO7jZ4M3B72kBS47keX9mFNLs/cMdqksIeaeUInW1bYTxACVc+zSXeu9mCTxSA1fVmKEI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=SsJwP2Zp; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=XruEIX07; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="SsJwP2Zp"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="XruEIX07" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66FE3Wl04097297 for ; Wed, 15 Jul 2026 14:10:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= rrdJsg/xINTNx7WBKUwZo/8lLXCAgU7OCvD1SQztacw=; b=SsJwP2Zpr4BciJEJ oKfYxBim4QlDRFxXmpTnxdVzyBOXMQuQWEopHfpLJg1nlY7LWnFyxAyKK+5rmOum hQqtI+OMZbE1xDmr3oQCwVZp+EwjQYv03fRMvCetIK152hrZH+qqJnUMYN94oVW4 4qszCcRtbakyhKlEjLXqz5FLADdSoDLLYx9OKid+y9Shy3ZA+Lzoa8Fly9Om74Jt 53N/d7L8asau9W5XzySsDnr61Ac3jOKwLeJ71cTBTQEi+6bjUZJ+uY+bSf46L/2i c7DyGUJrXUrMPEm3AsNk1aCIrROmPeeso/qnGTJm8XJflnGB9LPVmO1ouqknqzE3 mOg9Nw== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fe8558ygg-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 15 Jul 2026 14:10:52 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-c96b4f58ddcso2122806a12.3 for ; Wed, 15 Jul 2026 07:10:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784124651; x=1784729451; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=rrdJsg/xINTNx7WBKUwZo/8lLXCAgU7OCvD1SQztacw=; b=XruEIX07Mg7E2OMdAkTGE4BjHOK9bbea/9B4gFlU0pbdvfaZv1PhizLE6HyosGU0gh wweo2uPGfaInPuLGOOTe36xZ0jLPNpqGz6FwViM138R4CPUaI67N6uFr2ZU2Kf1/2Fo8 ZYGmw3MgUnhIK/ivRVrqGkk7xOi/UJuv6v/VRfkTy+Si8ClBIcpPSkO9lgj6Jafdwc+H +kmp7bnS4yW24vTfMdr3DoLmrMcRN+WeMVD3b+nBy9BG2J9G4t784wj5/YqU3/r/HOnE YDna9AvhtmEgd3YFP+Ay3lG/CFn25FGF0Ltf3feP6ZYWWPmSDLmFa8WpEj052Z7BjJaZ 5xIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784124651; x=1784729451; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=rrdJsg/xINTNx7WBKUwZo/8lLXCAgU7OCvD1SQztacw=; b=Rs8CfUINvh5ET7slB5Jujb1h8NFAa18DYRAiN49qL4TOe5JTuEXbkKRSNXbASvg591 rH21JFoXqiOwmNZ91pxCl30RKYYB4c19EU/ID9HHGvA0TCxJAH4AHDmvFsNwyhrq91mK pWoRh/4gXtXvdX8+4ElJS5Lt4Z3gKkVTM3DTylSNI05Wb6SfUR5h6u+kPbV4a7qo+mFt bZ1l/2jxjcbBDwKAB7m897umsySCmnS/w0p5AdiMXfIGsHjVEJpWJmQgckyRK4AvVQX0 4mTIYVmDDbRmPFIBEU95k9kN4/g7f/3b6eZ9znnSr0tKfR9bcNXM7MO0E5IoanMUPWKd vWWA== X-Gm-Message-State: AOJu0Yxed3KuLBDwPeU4F7CRnoCfTNx+Fexg3qoOGyDEUGEPXqnRlJQC EPhfQBfvovPajGC1QuQTel/+iM2Hir8ioaJkT8p2P6MpAtCCqdNSv4V64Xh17XtX7h12V1Ra/Sz qk5QTrP4IFsmBaluAODt7iRW8XCTDWjMyhdMhhpSttZ5oEUSxUodJ2pWzzH33P+utolqjQ+uOvb o= X-Gm-Gg: AfdE7cl9b6NRZCyssSXEM/33GpDlIfEmPe5NY3YgwxA2PwPFTIfrMlupyKyvdhkN0qP +L5ldBOCSifDlKUO+ASuytxy9KyssnyV3Rc50se/IbJJ0J6505qwwA1m5WISURptXnmIKYBShzD QtR+vf3bhydFj2ZW2qbdqPU1iWhFx0HbGB2dpl8LRXLlPFs7uxgy4X9eRnsynnHA2smpKFRh54O fS72Kqa0/TVqChn/u+lO+CT7sqdEmK6/BHXaHm2ih0K12+6aOtLk30cktJ7nXyvxOlm3MpPAOa5 5JIr/PwJ0DrA9qbMv25RIeZ2/VKC6jgP3XU/tsfni4dryXGtR0zMlEbcpCjdBCgsRpErHv/J4i+ uedEfARaaNbFZH0PIA9704pIwOcqqomhn088ZoJ0m+0XT X-Received: by 2002:a17:903:388c:b0:2cc:9773:1313 with SMTP id d9443c01a7336-2ce9ebf84f7mr162566995ad.11.1784124651292; Wed, 15 Jul 2026 07:10:51 -0700 (PDT) X-Received: by 2002:a17:903:388c:b0:2cc:9773:1313 with SMTP id d9443c01a7336-2ce9ebf84f7mr162566465ad.11.1784124650754; Wed, 15 Jul 2026 07:10:50 -0700 (PDT) Received: from hu-bvisredd-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cf1070b68dsm2913215ad.79.2026.07.15.07.10.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 07:10:50 -0700 (PDT) From: Vishnu Reddy Date: Wed, 15 Jul 2026 19:40:00 +0530 Subject: [PATCH v9 06/14] media: iris: Enable Secure PAS support with IOMMU managed by Linux Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260715-glymur-v9-6-8cf2cbe12a07@oss.qualcomm.com> References: <20260715-glymur-v9-0-8cf2cbe12a07@oss.qualcomm.com> In-Reply-To: <20260715-glymur-v9-0-8cf2cbe12a07@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Dmitry Baryshkov , Mauro Carvalho Chehab , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanimir Varbanov , Bjorn Andersson , Konrad Dybcio Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, Vishnu Reddy , Mukesh Ojha X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784124602; l=7611; i=busanna.reddy@oss.qualcomm.com; s=20260216; h=from:subject:message-id; bh=Wuzgz1rzYvmDPB16a5Puzh+s48WQEHTanWtzd6CqHlE=; b=odkLVJ4nr2zh2Z+CcxNiUkSjlLIjbEJAXhQ1GWbxqSD1k9DkP4ivWYWIYf1kfAlbH2uZ6Q8y7 arzPAi5rPLwAw8+W8GONX/QbpMg2zWInOYrEwk1O9HXmrc+jEcvSA4/ X-Developer-Key: i=busanna.reddy@oss.qualcomm.com; a=ed25519; pk=9vmy9HahBKVAa+GBFj1yHVbz0ey/ucIs1hrlfx+qtok= X-Proofpoint-GUID: I-K3sxyu5xBcdkA9U0n67reJPQnqJgu9 X-Authority-Analysis: v=2.4 cv=KOlqylFo c=1 sm=1 tr=0 ts=6a5794ec cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=U8OLdchxA3Z7P0hrdlYA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE1MDE0MSBTYWx0ZWRfX5ooSzgp3P6df ViDRoqH7xxM138y8fkGLgGSk9GFS1t+/eX7HDWz9S4dfFTMd0FLPJKXTvdd2NI3gQuCyJp+Yh9Y L4rcAqZzPv4GlUTxuyy9Sr4YRIsTyGb1K9OANhjBXRBXs/+WnO8pgoUH9eqS2iLW9dOpMgiNqPd b9lyGwI6vqROtB7WUmSlVuGDjL/lj4/oCcI08dY29y1S4owJS0Q3pdZNwiZmDIs1l/SCmtiYbcB HMR/dymycXth+COgQX+GclnnfXtPpwvB/LhN0U4qme79vXIql8fnG8efz1nR3corRzmwsACQUfS PTldJ7Xo1tZUbdzoUtu/O9YpFKqrxPkDRypfa0YHZAO6tXyfxk92OGuz+NDGi+xIoRnUHyXFLeJ whFJ/A0rhpB9fLgmM0zxR463Y14EWjYSMQrP23j+J67skdONs4YDra0xeEScgUu5wUWRU3GZwDo sRs0dt3TV0jhKdUuJ+Q== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE1MDE0MSBTYWx0ZWRfX/G/cPj98IPs1 htEZJevLL2xM93HhiSmi6x7mis4mmjP0EJoaq5EBDv5t9ihUrTEjPqwxrnL7ue+KO5Uq4nRjeLm bxhr0/8z/aa4hy9EQ5RMeKDxjd5Sa/U= X-Proofpoint-ORIG-GUID: I-K3sxyu5xBcdkA9U0n67reJPQnqJgu9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-15_03,2026-07-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 impostorscore=0 malwarescore=0 spamscore=0 clxscore=1015 priorityscore=1501 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607150141 From: Mukesh Ojha On platforms where a hypervisor is present, all Secure Monitor Calls (SMC) are intercepted. For qcom_scm_pas_auth_and_reset(), the hypervisor registers a Shared Memory (SHM) bridge over the Peripheral Image Loader (PIL) memory region so that TrustZone (TZ) can access it, forwards the authentication SMC to TZ, and upon return maps the PIL region and triggers the co-processor bring-up sequence: HLOS -> Hypervisor(SHM setup) -> TZ(auth) -> Hypervisor(map+reset) -> IRIS On platforms without a hypervisor, Linux drives these steps directly. The SHM bridge infrastructure required for this is already upstream [1]. To isolate firmware memory in its own Input-Output Memory Management Unit (IOMMU) context, a dedicated stream ID (SID) is required, tied to the firmware function ID. This SID is specified via the iommu-map property in the device tree using the firmware function ID as the lookup key. A firmware device is created and mapped to this SID. The presence of a SID mapped to the firmware device via iommu-map is used to detect whether a hypervisor is absent: when the firmware device has a SID mapped, Linux manages the IOMMU directly; when no SID is mapped, a hypervisor is assumed to be present and these steps are skipped. Extend the Iris driver to support Secure Peripheral Authentication Service (PAS) on platforms where Linux manages the IOMMU, by creating the firmware context device and performing the necessary IOMMU mapping when the firmware device SID is present. [1] https://lore.kernel.org/lkml/20260105-kvmrprocv10-v10-0-022e96815380 @oss.qualcomm.com/ Reviewed-by: Vishnu Reddy Co-developed-by: Vikash Garodia Signed-off-by: Vikash Garodia Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/lkml/20260105-kvmrprocv10-v10-0-022e96815380@oss.qualcomm.com/ Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/iris_core.h | 4 ++ drivers/media/platform/qcom/iris/iris_firmware.c | 73 ++++++++++++++++++++---- 2 files changed, 65 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/platform/qcom/iris/iris_core.h index 3c96f46cf567..5ed2ec0b97ec 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -38,6 +38,8 @@ struct qcom_ubwc_cfg_data; * @dev: reference to device structure * @np_dev: reference to non-pixel device structure * @p_dev: reference to pixel device structure + * @fw_dev: reference to firmware device structure + * @pas_ctx: PAS context for authenticated firmware load and shutdown * @reg_base: IO memory base address * @irq: iris irq * @v4l2_dev: a holder for v4l2 device structure @@ -85,6 +87,8 @@ struct iris_core { struct device *dev; struct device *np_dev; struct device *p_dev; + struct device *fw_dev; + struct qcom_pas_context *pas_ctx; void __iomem *reg_base; int irq; struct v4l2_device v4l2_dev; diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c index 1a476146d758..56c477b36b61 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -4,7 +4,9 @@ */ #include +#include #include +#include #include #include #include @@ -15,11 +17,14 @@ #define IRIS_PAS_ID 9 #define MAX_FIRMWARE_NAME_SIZE 128 +#define IRIS_FW_START_ADDR 0 static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) { + struct device *fw_dev = core->fw_dev ? core->fw_dev : core->dev; const struct firmware *firmware = NULL; - struct device *dev = core->dev; + struct qcom_pas_context *ctx; + struct iommu_domain *domain; struct resource res; phys_addr_t mem_phys; size_t res_size; @@ -30,14 +35,21 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) if (strlen(fw_name) >= MAX_FIRMWARE_NAME_SIZE - 4) return -EINVAL; - ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res); + ret = of_reserved_mem_region_to_resource(core->dev->of_node, 0, &res); if (ret) return ret; mem_phys = res.start; res_size = resource_size(&res); - ret = request_firmware(&firmware, fw_name, dev); + if (!core->pas_ctx) { + ctx = devm_qcom_pas_context_alloc(core->dev, IRIS_PAS_ID, mem_phys, res_size); + if (IS_ERR(ctx)) + return PTR_ERR(ctx); + core->pas_ctx = ctx; + } + + ret = request_firmware(&firmware, fw_name, fw_dev); if (ret) return ret; @@ -53,9 +65,23 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) goto err_release_fw; } - ret = qcom_mdt_load(dev, firmware, fw_name, - IRIS_PAS_ID, mem_virt, mem_phys, res_size, NULL); + core->pas_ctx->use_tzmem = !!core->fw_dev; + ret = qcom_mdt_pas_load(core->pas_ctx, firmware, fw_name, mem_virt, NULL); + if (ret) + goto err_mem_unmap; + + if (core->pas_ctx->use_tzmem) { + domain = iommu_get_domain_for_dev(fw_dev); + if (!domain) { + ret = -ENODEV; + goto err_mem_unmap; + } + + ret = iommu_map(domain, IRIS_FW_START_ADDR, mem_phys, res_size, + IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); + } +err_mem_unmap: memunmap(mem_virt); err_release_fw: release_firmware(firmware); @@ -63,6 +89,18 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) return ret; } +static void iris_fw_iommu_unmap(struct iris_core *core) +{ + struct iommu_domain *domain; + + if (!core->fw_dev) + return; + + domain = iommu_get_domain_for_dev(core->fw_dev); + if (domain) + iommu_unmap(domain, IRIS_FW_START_ADDR, core->pas_ctx->mem_size); +} + int iris_fw_load(struct iris_core *core) { const struct tz_cp_config *cp_config; @@ -77,13 +115,13 @@ int iris_fw_load(struct iris_core *core) ret = iris_load_fw_to_memory(core, fwpath); if (ret) { dev_err(core->dev, "firmware download failed\n"); - return -ENOMEM; + return ret; } - ret = qcom_scm_pas_auth_and_reset(IRIS_PAS_ID); + ret = qcom_pas_prepare_and_auth_reset(core->pas_ctx); if (ret) { dev_err(core->dev, "auth and reset failed: %d\n", ret); - return ret; + goto err_unmap; } for (i = 0; i < core->iris_platform_data->tz_cp_config_data_size; i++) { @@ -94,20 +132,31 @@ int iris_fw_load(struct iris_core *core) cp_config->cp_nonpixel_size); if (ret) { dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret); - qcom_scm_pas_shutdown(IRIS_PAS_ID); - return ret; + goto err_pas_shutdown; } } + return 0; + +err_pas_shutdown: + qcom_pas_shutdown(IRIS_PAS_ID); +err_unmap: + iris_fw_iommu_unmap(core); + return ret; } int iris_fw_unload(struct iris_core *core) { - return qcom_scm_pas_shutdown(IRIS_PAS_ID); + int ret; + + ret = qcom_pas_shutdown(IRIS_PAS_ID); + iris_fw_iommu_unmap(core); + + return ret; } int iris_set_hw_state(struct iris_core *core, bool resume) { - return qcom_scm_set_remote_state(resume, 0); + return qcom_pas_set_remote_state(resume, 0); } -- 2.34.1