From: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Frank Li <Frank.Li@nxp.com>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>
Cc: devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Peng Fan <peng.fan@nxp.com>
Subject: [PATCH 1/9] arm64: dts: imx8ulp: Add DMA channel properties and use eDMA flag macros
Date: Wed, 15 Jul 2026 20:33:02 +0800 [thread overview]
Message-ID: <20260715-imx8ulp-dts-v1-1-19651358b599@nxp.com> (raw)
In-Reply-To: <20260715-imx8ulp-dts-v1-0-19651358b599@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
Add DMA channel (dmas/dma-names) properties to peripheral nodes that
were missing them:
- LPI2C: lpi2c4, lpi2c5, lpi2c6, lpi2c7
- LPUART: lpuart4, lpuart5, lpuart6, lpuart7
- LPSPI: lpspi4, lpspi5
Also replace hardcoded numeric DMA direction flags with the proper
FSL_EDMA_RX and FSL_EDMA_MULTI_FIFO macros for SAI (sai4, sai5, sai6,
sai7) and SPDIF nodes.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 32 +++++++++++++++++++++++++-----
1 file changed, 27 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index c6d1bb9edf388..5438958176985 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/imx8ulp-clock.h>
+#include <dt-bindings/dma/fsl-edma.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/imx8ulp-power.h>
@@ -370,6 +371,8 @@ lpi2c4: i2c@29370000 {
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
+ dmas = <&edma1 46 0 0>, <&edma1 45 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -383,6 +386,8 @@ lpi2c5: i2c@29380000 {
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
+ dmas = <&edma1 48 0 0>, <&edma1 47 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -392,6 +397,8 @@ lpuart4: serial@29390000 {
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
clock-names = "ipg";
+ dmas = <&edma1 55 0 FSL_EDMA_RX>, <&edma1 56 0 0> ;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -401,6 +408,8 @@ lpuart5: serial@293a0000 {
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
clock-names = "ipg";
+ dmas = <&edma1 57 0 FSL_EDMA_RX>, <&edma1 58 0 0> ;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -416,6 +425,8 @@ lpspi4: spi@293b0000 {
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
+ dmas = <&edma1 64 0 0>, <&edma1 63 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -431,6 +442,8 @@ lpspi5: spi@293c0000 {
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
+ dmas = <&edma1 66 0 0>, <&edma1 65 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
status = "disabled";
};
};
@@ -474,6 +487,8 @@ lpi2c6: i2c@29840000 {
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
+ dmas = <&edma1 50 0 0>, <&edma1 49 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -487,6 +502,8 @@ lpi2c7: i2c@29850000 {
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
+ dmas = <&edma1 52 0 0>, <&edma1 51 0 FSL_EDMA_RX>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -496,6 +513,8 @@ lpuart6: serial@29860000 {
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
clock-names = "ipg";
+ dmas = <&edma1 59 0 FSL_EDMA_RX>, <&edma1 60 0 0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -505,6 +524,8 @@ lpuart7: serial@29870000 {
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
clock-names = "ipg";
+ dmas = <&edma1 61 0 FSL_EDMA_RX>, <&edma1 62 0 0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -516,7 +537,7 @@ sai4: sai@29880000 {
<&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
- dmas = <&edma1 67 0 1>, <&edma1 68 0 0>;
+ dmas = <&edma1 67 0 FSL_EDMA_RX>, <&edma1 68 0 0>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
fsl,dataline = <0 0x03 0x03>;
@@ -531,7 +552,7 @@ sai5: sai@29890000 {
<&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
- dmas = <&edma1 69 0 1>, <&edma1 70 0 0>;
+ dmas = <&edma1 69 0 FSL_EDMA_RX>, <&edma1 70 0 0>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
fsl,dataline = <0 0x0f 0x0f>;
@@ -814,7 +835,7 @@ sai6: sai@2da90000 {
<&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
- dmas = <&edma2 71 0 1>, <&edma2 72 0 0>;
+ dmas = <&edma2 71 0 FSL_EDMA_RX>, <&edma2 72 0 0>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
fsl,dataline = <0 0x0f 0x0f>;
@@ -829,7 +850,7 @@ sai7: sai@2daa0000 {
<&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
- dmas = <&edma2 73 0 1>, <&edma2 74 0 0>;
+ dmas = <&edma2 73 0 FSL_EDMA_RX>, <&edma2 74 0 0>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
fsl,dataline = <0 0x0f 0x0f>;
@@ -855,7 +876,8 @@ spdif: spdif@2dab0000 {
"rxtx3", "rxtx4",
"rxtx5", "rxtx6",
"rxtx7", "spba";
- dmas = <&edma2 75 0 5>, <&edma2 76 0 4>;
+ dmas = <&edma2 75 0 (FSL_EDMA_RX | FSL_EDMA_MULTI_FIFO)>,
+ <&edma2 76 0 FSL_EDMA_MULTI_FIFO>;
dma-names = "rx", "tx";
status = "disabled";
};
--
2.34.1
next prev parent reply other threads:[~2026-07-15 12:30 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-15 12:33 [PATCH 0/9] arm64: dts: imx8ulp: Device tree updates for i.MX 8ULP EVK boards Peng Fan (OSS)
2026-07-15 12:33 ` Peng Fan (OSS) [this message]
2026-07-15 12:33 ` [PATCH 2/9] arm64: dts: imx8ulp: Add I3C2 controller node Peng Fan (OSS)
2026-07-15 12:33 ` [PATCH 3/9] arm64: dts: imx8ulp: Correct SRAM node address and size to cover full SSRAM P2 Peng Fan (OSS)
2026-07-15 12:33 ` [PATCH 4/9] arm64: dts: imx8ulp: Add assigned clock properties for LPUART nodes Peng Fan (OSS)
2026-07-15 12:33 ` [PATCH 5/9] arm64: dts: imx8ulp-evk: Add gpio-keys node for power button Peng Fan (OSS)
2026-07-15 12:33 ` [PATCH 6/9] arm64: dts: imx8ulp-evk: Enable LPUART6 for Bluetooth Peng Fan (OSS)
2026-07-15 15:17 ` Frank Li
2026-07-15 12:33 ` [PATCH 7/9] arm64: dts: imx8ulp-evk: Enable LPUART7 Peng Fan (OSS)
2026-07-15 15:18 ` Frank Li
2026-07-15 12:33 ` [PATCH 8/9] arm64: dts: imx8ulp-evk: Change the values of some PCRs of ENET Peng Fan (OSS)
2026-07-15 12:33 ` [PATCH 9/9] arm64: dts: imx8ulp-9x9-evk: Rename model string to reflect die size Peng Fan (OSS)
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