From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 20BDC283FCE for ; Wed, 15 Jul 2026 05:34:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093676; cv=none; b=hB4CzX+TO9lZyHzHpVFi0GQx6Jl5XotElE1V6LYRpkg7BuliL4va07cdewSJ9A+8yMqC5lEFte9RiVmyPLB/34njnIuAtgsJb2MHe5vL7iNzYktaEnVBZPM3QO3tZgcL8mCBQud5M9yLIMHpgMRDEFeHEwn4lc1P9ajC3Ar1jrw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093676; c=relaxed/simple; bh=uwJV+EsB0lwOLAI7SAT6zxl/zg4JX03Zlp6o4bG1BNY=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=DtfopINqUdwgOf/K38Fci5+CfSOsGT8JqSm3kqeg8dj8+oRZSRswHW4RfMGz3qBWsy02w7Dfy0hSAeZvoAbxJ3qACyYlV/SBn0eofw0TaGIfQHDqaaCJhnqudFjHW6OWUUZeWv5qVrbGkH6ilCgwpEQpq+ZhTmhqHgU3clUSK+M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=lteo+As5; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="lteo+As5" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0FD39339; Tue, 14 Jul 2026 22:34:28 -0700 (PDT) Received: from a079125.blr.arm.com (a079125.arm.com [10.164.21.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6537E3F915; Tue, 14 Jul 2026 22:34:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784093672; bh=uwJV+EsB0lwOLAI7SAT6zxl/zg4JX03Zlp6o4bG1BNY=; h=From:To:Cc:Subject:Date:From; b=lteo+As5uQ6WqmOCAjra1YlPd9gItBMt/iEnjyacnFqCM1RAuC03P+3kX226O9Bte TPdo/AH93nsVUzE3ScJG980b5pXq9q8vOrMcumWgXQwcDf4u/8CcwUTnhJlYvsmZnC m5IP54mflHUUe5pvvBz2DLJXoHrT2CHXuJz/JvA0= From: Linu Cherian To: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linu Cherian Subject: [PATCH v3 0/6] Add BBML3 cpu feature Date: Wed, 15 Jul 2026 11:04:02 +0530 Message-ID: <20260715053408.1950475-1-linu.cherian@arm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit - Patches 1, 2 and 3 adds more cpus to the bbml2_noabort support list. bbml2_noabort would eventually gets renamed to bbml3 in a subsequent patch as they are functionally equivalent. - Patches 4, 5 & 6 introduces BBML3 cpu feature Changelog from v2: * Added errata id to Documentation/arch/arm64/silicon-errata.rst in patch 3. Added comments in code related to errata as well. * Fixed register name typo in commit message in patch 4. * Renamed patch title in patch 5. * Commit message reworded in patch 6. * No functional changes in this version. Changelog from v1: * Patches associated with adding cpus to BBML2_NOABORT, support list, were kept at bottom in v1 is now moved up in this version, for ease of backporting. * Adding BBM_3 definition in sysreg moved into a separate patch * MMFR2_ID check for BBM_3 has been changed from == BBM_3 to >= BBM_3, so that BBML3 cpu feature gets enabled for BBM_4 as well. * For feature detection, MMFR2_ID check comes first followed by midr check for code readability * Errata details for C1-Ultra and C1-Premium added to commit message Linu Cherian (6): arm64: cputype: Add Cortex-A520AE definitions arm64: cputype: Add C1-Nano definitions arm64: cpufeature: Extend bbml2_noabort support list arm64: sysreg: Add BBM_3 arm64: cpufeature: Rename BBML2_NOABORT as BBML3 arm64: cpufeature: Detect BBML3 based on ID_AA64MMFR2_EL1.BBM Documentation/arch/arm64/silicon-errata.rst | 4 ++ arch/arm64/include/asm/cpufeature.h | 6 +-- arch/arm64/include/asm/cputype.h | 4 ++ arch/arm64/kernel/cpufeature.c | 55 ++++++++++----------- arch/arm64/mm/contpte.c | 21 +++----- arch/arm64/mm/mmu.c | 52 +++++++++---------- arch/arm64/mm/proc.S | 4 +- arch/arm64/tools/cpucaps | 2 +- arch/arm64/tools/sysreg | 1 + 9 files changed, 76 insertions(+), 73 deletions(-) -- 2.43.0