From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 465633B47F3 for ; Wed, 15 Jul 2026 05:34:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093678; cv=none; b=Qcf4R2NEeBVPKaffbzY4F20z9wmM22TdgvILOCYrstn3byabwLgMjP2rB4ZGqTFJX7PvUDprmLpeVLmOH/9suGdHeJUFkzl9E9WFXfFcXEEOxXS4DjgsMBD3EB3UnMlX1asuT3GaAG7dxgRsG3smaXHTWL1IKB82BYUOXaUhjZQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093678; c=relaxed/simple; bh=mF5BRgQuHu/yR1NXlAdo4m6cZY21TPxbdISvRvl9Lmk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CoeQrwumE+s+LlL/Hvjezv2jU/ZfeQPETu/37CSEDGbL8ON6GxSo6AOjtIp9/3/nvx2cV0Hd8iEhmmpnTxQ6NuwVfGswtqWtfrePJeQSGAA+oZm86arWI9b3aROZ/RHhBeIybCBtIKg3qKBO/51SZ6PTOfgvyDuDkm78pxZbZhs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=pTZX4po8; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="pTZX4po8" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 583A81477; Tue, 14 Jul 2026 22:34:31 -0700 (PDT) Received: from a079125.blr.arm.com (a079125.arm.com [10.164.21.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B082C3F915; Tue, 14 Jul 2026 22:34:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784093675; bh=mF5BRgQuHu/yR1NXlAdo4m6cZY21TPxbdISvRvl9Lmk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pTZX4po81HuHAmi//UY5p/Ukhb6eQpLf9m2KT/WmRwuvUrVF6EkBv6qvuFAbitcUI Qew8OLdXi34BsXesqsWy8PaFa6v/kwbC2oNuCOQc0eoNZ09ZJFbzK4J5AeiYl33b9f OOgUE6LeADK/gd9d5IYRhJ2iNQwm79O9J2IBTZ4o= From: Linu Cherian To: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linu Cherian Subject: [PATCH v3 1/6] arm64: cputype: Add Cortex-A520AE definitions Date: Wed, 15 Jul 2026 11:04:03 +0530 Message-ID: <20260715053408.1950475-2-linu.cherian@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715053408.1950475-1-linu.cherian@arm.com> References: <20260715053408.1950475-1-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add cputype definitions for Cortex-A520AE. The definition can be found in Cortex-A520AE TRM, https://developer.arm.com/documentation/107726/0001/ as part of MIDR_EL1 bit descriptions. This is going to be used in the bbml3 support list. Reviewed-by: Anshuman Khandual Signed-off-by: Linu Cherian --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 1b9f0cda1336..e41fae46426b 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -82,6 +82,7 @@ #define ARM_CPU_PART_CORTEX_X1 0xD44 #define ARM_CPU_PART_CORTEX_A510 0xD46 #define ARM_CPU_PART_CORTEX_A520 0xD80 +#define ARM_CPU_PART_CORTEX_A520AE 0xD88 #define ARM_CPU_PART_CORTEX_A710 0xD47 #define ARM_CPU_PART_CORTEX_A715 0xD4D #define ARM_CPU_PART_CORTEX_X2 0xD48 @@ -176,6 +177,7 @@ #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) #define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520) +#define MIDR_CORTEX_A520AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520AE) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715) #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) -- 2.43.0