From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D42C03B47DD for ; Wed, 15 Jul 2026 05:34:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093684; cv=none; b=AIwFYvjBtwK5HVKhT593xBBdlOQwBD2B+uV455p1tm3XosPD9ZUBDEhm6tK6aHYOdMvvszLfaOjFw3E6HpItzx9c0qhwerQHZ3FxXyA/pmFz2dYPfJ364nkr0qObnlDHTG+faaeB4A6ANVX3u7tCghOUuUMy5sNf2VFSeT/jilw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093684; c=relaxed/simple; bh=N7dBfVaI7343acB0SSAtsxc3PMX1dKExbRDxnREghp8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=F73qAxnaMprTB1//LSIOshjT7bA6cx+wtcziJk8D12Ptd1ctcOPuAtaCS+aGn/UvTcRazmCAU3Ws6P/WM58FZBpRwMQ2L3BoaO7ccxk//PgT64PlVMdzQOnCKFvTYAH7MwouY9NBkidhsgQLKqk+dm/BJpnm9nKtOBhVs/Ev3p8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=bl0S0hqs; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="bl0S0hqs" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EB0AD339; Tue, 14 Jul 2026 22:34:37 -0700 (PDT) Received: from a079125.blr.arm.com (a079125.arm.com [10.164.21.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 51B653F915; Tue, 14 Jul 2026 22:34:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784093682; bh=N7dBfVaI7343acB0SSAtsxc3PMX1dKExbRDxnREghp8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bl0S0hqs9IXXWEHjjCVDLxRM8UWFJU6CjYBItjLLAwKtip/UTC3HUWo4NWPBawb2h 0zybto25wB65R7tUiRHUdLwroi6BFRLXKE8OxlvLti+p2l5I1GgpHwgFGHBeME8Zje ehoR1W3FEdx4hAaMh3xS4VpsOyzxY+tN3tDJi6QE= From: Linu Cherian To: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linu Cherian Subject: [PATCH v3 3/6] arm64: cpufeature: Extend bbml2_noabort support list Date: Wed, 15 Jul 2026 11:04:05 +0530 Message-ID: <20260715053408.1950475-4-linu.cherian@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715053408.1950475-1-linu.cherian@arm.com> References: <20260715053408.1950475-1-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add below cpus to the midr list, which supports BBML2_NOABORT. Cortex A520(AE) Cortex A715 Cortex A720(AE) Cortex A725 Neoverse N3 C1-Nano C1-Pro C1-Ultra C1-Premium C1-Ultra and C1-Premium both suffer from erratum 3683289, where Break-Before-Make must be followed to avoid a livelock. For both CPUs, the erratum is fixed from r1p1. Hence we do not enable BBML2_NOABORT for CPU revisions <= r1p0. The relevant SDENs are: * C1-Ultra: https://developer.arm.com/documentation/111077/9-00/ * C1-Premium: https://developer.arm.com/documentation/111078/9-00/ Signed-off-by: Linu Cherian --- Documentation/arch/arm64/silicon-errata.rst | 4 ++++ arch/arm64/kernel/cpufeature.c | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index 014aa1c215a1..57c778446936 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -242,10 +242,14 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-V3AE | #4193784 | ARM64_ERRATUM_4118414 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | C1-Premium | #3683289 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | C1-Premium | #4193780 | ARM64_ERRATUM_4118414 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | C1-Pro | #4193714 | ARM64_ERRATUM_4193714 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | C1-Ultra | #3683289 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | C1-Ultra | #4193780 | ARM64_ERRATUM_4118414 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | MMU-500 | #562869, | ARM_SMMU_MMU_500_CPRE_ERRATA| diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9a22df0c5120..1b804b6c4fe0 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2152,6 +2152,16 @@ bool cpu_supports_bbml2_noabort(void) MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), MIDR_ALL_VERSIONS(MIDR_AMPERE1), MIDR_ALL_VERSIONS(MIDR_AMPERE1A), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), + MIDR_ALL_VERSIONS(MIDR_C1_NANO), + MIDR_ALL_VERSIONS(MIDR_C1_PRO), + /* Erratum 3683289 fixed in r1p1 */ + MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf), + MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf), {} }; -- 2.43.0