From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B32C93B38AB for ; Wed, 15 Jul 2026 05:34:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093695; cv=none; b=VD3Tx2FEXB68cTxwWYTCSXX14uTB1qbPb30+SRsjZ7kaDj6BMLF1xhVS21eXZhfyz2AfIE7UwbPzf8cOD0xXdVL5jdjKhbXyB0A5R8oXdfMkbnBpoX+iGgbQpuHKfDM6jUYcnZUbNY25bcxAw20sBRai/lnXrYUqgZWMU5Xo4EY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093695; c=relaxed/simple; bh=xvWUwM25jkFsnNcI43QGqVVl3Rwv1/DjKc78I+lBWqM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OnqZlQtgIcevLCPFfy+ovQYfgDXM0i7+6nnCgFdoAFQzE8ptBJ+mrpWGgb4K2veFRnPQCXbunGEfOkMr2WcwvLlwvB0/rliuCX8GSZuFdwfYNchnsenR1J3HR0FhfWhmJoJjmMRXkJR8EVquC5eSKpMMn9GOtoCfsGppML/ZmRw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=G6wCkvGs; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="G6wCkvGs" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6B109339; Tue, 14 Jul 2026 22:34:48 -0700 (PDT) Received: from a079125.blr.arm.com (a079125.arm.com [10.164.21.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 470B03F915; Tue, 14 Jul 2026 22:34:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784093692; bh=xvWUwM25jkFsnNcI43QGqVVl3Rwv1/DjKc78I+lBWqM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G6wCkvGskLePoHKA/n5nuizoDjgIdhGsDiSi3elStoMYQC4zdex8jP1EUeY+hP31m rsG3ez2hhDTlfLx2R3dkI5F0z8/ftZMguLrkAmRQuXKzhjTE9hyjVEvv61G5jRtSc4 qCo7QfHply7l6I7LieH2S16Taxc2vrr3MgB6COVo= From: Linu Cherian To: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linu Cherian Subject: [PATCH v3 6/6] arm64: cpufeature: Detect BBML3 based on ID_AA64MMFR2_EL1.BBM Date: Wed, 15 Jul 2026 11:04:08 +0530 Message-ID: <20260715053408.1950475-7-linu.cherian@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715053408.1950475-1-linu.cherian@arm.com> References: <20260715053408.1950475-1-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add ID_AA64MMFR2_EL1.BBM based BBML3 feature detection in cpu_supports_bbml3() so that cpus with the feature would not have to be added into MIDR based supports_bbml3_list. Signed-off-by: Linu Cherian --- arch/arm64/kernel/cpufeature.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 25a705e02618..b58fdcb35406 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2133,6 +2133,12 @@ static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, bool cpu_supports_bbml3(void) { + u64 mmfr2; + + mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1); + if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) >= ID_AA64MMFR2_EL1_BBM_3) + return true; + /* CPUs that support BBML3 but dont advertise through MMFR2 ID */ static const struct midr_range supports_bbml3_list[] = { MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), @@ -2154,15 +2160,10 @@ bool cpu_supports_bbml3(void) {} }; - if (!is_midr_in_range_list(supports_bbml3_list)) - return false; - - /* - * We currently ignore the ID_AA64MMFR2_EL1 register, and only care - * about whether the MIDR check passes. - */ + if (is_midr_in_range_list(supports_bbml3_list)) + return true; - return true; + return false; } static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope) -- 2.43.0