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Wysocki" , Danilo Krummrich , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: Wei Deng , Chen-Yu Tsai , linux-acpi@vger.kernel.org, driver-core@lists.linux.dev, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Alan Stern Subject: [PATCH v5 15/16] arm64: dts: mediatek: mt8195-cherry: Add M.2 E-key slot Date: Wed, 15 Jul 2026 16:53:45 +0800 Message-ID: <20260715085348.3457359-16-wenst@chromium.org> X-Mailer: git-send-email 2.55.0.141.g00534a21ce-goog In-Reply-To: <20260715085348.3457359-1-wenst@chromium.org> References: <20260715085348.3457359-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Mt8195 Cherry design features an M.2 E-key slot for WiFi/BT combo cards. Only PCIe and USB are wired from the SoC to the slot, along with some auxiliary signals. Add the proper representation for it, replacing the PCIe wifi node and vpcie3v3-supply property under the PCIe controller, and the vbus-supply property under the xhci3 node. Signed-off-by: Chen-Yu Tsai --- Changes since v2: - Drop default GPIO output state from kill pins pinconfig --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 73 +++++++++++++++++-- 1 file changed, 68 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index ef7afc436aef..8d4cc30d91e4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -266,6 +266,47 @@ tboard_thermistor2: thermal-sensor-t2 { 120000 51 125000 44>; }; + + wifi-bt-connector { + compatible = "pcie-m2-e-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&m2_e_key_kill_pins>; + vpcie3v3-supply = <&pp3300_wlan>; + w-disable1-gpios = <&pio 61 GPIO_ACTIVE_LOW>; + w-disable2-gpios = <&pio 59 GPIO_ACTIVE_LOW>; + /* PCIe auxiliary signals wired to controller. */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* PCIe for WiFi */ + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + wifi_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&pcie1_ep>; + }; + }; + + /* USB for Bluetooth */ + port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + bt_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&usb3_ep>; + }; + }; + + /* SDIO, UART and I2S not implemented */ + }; + }; }; &adsp { @@ -791,14 +832,14 @@ pcie@0 { reg = <0 0 0 0 0>; device_type = "pci"; num-lanes = <1>; - vpcie3v3-supply = <&pp3300_wlan>; #address-cells = <3>; #size-cells = <2>; ranges; - wifi@0 { - reg = <0 0 0 0 0>; - wakeup-source; + port { + pcie1_ep: endpoint { + remote-endpoint = <&wifi_ep>; + }; }; }; }; @@ -1085,6 +1126,13 @@ pins-bus { }; }; + m2_e_key_kill_pins: m2-e-key-kill-pins { + pins-kill { + pinmux = , + ; + }; + }; + mmc0_pins_default: mmc0-default-pins { pins-cmd-dat { pinmux = , @@ -1637,9 +1685,24 @@ &xhci2 { &xhci3 { /* MT7921's USB Bluetooth has issues with USB2 LPM */ usb2-lpm-disable; - vbus-supply = <&pp3300_wlan>; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + usb3_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&bt_ep>; + }; + }; + }; }; #include -- 2.55.0.795.g602f6c329a-goog