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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13cd42b2c0bsm471669c88.8.2026.07.15.04.16.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 04:16:29 -0700 (PDT) From: Wei Deng To: mani@kernel.org Cc: dmitry.baryshkov@oss.qualcomm.com, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, brgl@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, wenst@chromium.org, mengshi.wu@oss.qualcomm.com, quic_chezhou@quicinc.com, cheng.jiang@oss.qualcomm.com, shuai.zhang@oss.qualcomm.com, jinwang.li@oss.qualcomm.com, xiuzhuo.shang@oss.qualcomm.com Subject: Re: [PATCH 3/3] power: sequencing: pcie-m2: Deassert W_DISABLE2# when no UART serdev is created Date: Wed, 15 Jul 2026 16:46:22 +0530 Message-Id: <20260715111622.2561730-1-wei.deng@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE1MDEwOSBTYWx0ZWRfX05yLjLUChjtF QTzvKn12dV7mQGe3riEx8M7QgKz+/jEafqJVIWRHcgMBcu3fvBMRDmA7qSbQ5pu4JT9oQ/K1Rca eeJHsAwXWLq1Q4uoQTK7nu/t+b9E+LM= X-Proofpoint-ORIG-GUID: LOjloL2t9125B96X7q8ROj7x1xannctm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE1MDEwOSBTYWx0ZWRfX5zHI+0zSDAjq urQe3RiuXT3cywr6JtymgUds1V/bvhTMrmSXaU4UqVjYGW2Owsl30405CWSeIZOQylahQHHudpX 55DYVls0VDi0S1iwKtGPC2gOa5fV7wSniXiG5R2LeFlqM10NGDCbz7A6EtLgJDdi72rR8RgwhPS 7FOMWxnKjaNPf7qxhVYONTfOHot2v8gZUpI9hJxjo9ih8T/APf9YvvfiP8Xnj54gElgbpWKoI39 IGdDCUZa+3EiWEule3YTY6dssMbsVck2jHVcY6DI7zyh2f0rYvIGcg63Lb7rnZI4AuJVJDEiipr c5V4M3h4zn4FK2LtWWL0obXb5wtzvy+sCbMDY78A2B2GVZgm9uuDi9H3bCWtZ7yZky1n0Rqa0TZ 1Dwoe883TKJZ30Nyyew0FX+pk/tUrvOColTp7kzKu147J4m++Tdn57W2gVFNmaXSw6EQM+hmxZh UNLyAp+ipeQkDuxqdqA== X-Proofpoint-GUID: LOjloL2t9125B96X7q8ROj7x1xannctm X-Authority-Analysis: v=2.4 cv=VoATxe2n c=1 sm=1 tr=0 ts=6a576c0f cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=VwQbUJbxAAAA:8 a=cm27Pg_UAAAA:8 a=RcxsvD7BqTzStQuQcmYA:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-15_02,2026-07-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607150109 On Tue, 14 Jul 2026, Manivannan Sadhasivam wrote: > On Mon, Jul 13, 2026 at 02:46:16PM +0530, Wei Deng wrote: > > On Thu, 9 Jul 2026, Dmitry Baryshkov wrote: > > > On Thu, Jul 09, 2026 at 12:59:42PM +0530, Wei Deng wrote: > > > > The pwrseq_m2_pci_ids[] table lists PCIe BT devices that use UART as the > > > > BT transport and need a UART serdev created by the driver. When a PCIe > > > > device under the M.2 connector does not match any entry in this table, > > > > no UART serdev is created. > > > > > > > > However, the BT subsystem of such a device may still require W_DISABLE2# > > > > to be deasserted to power up. Rather than adding every possible non-UART > > > > BT device ID to the table, add an else branch that deasserts W_DISABLE2# > > > > whenever a PCIe device is detected under the connector but does not match > > > > a UART BT entry. This allows any BT interface on the card (USB or other) > > > > to enumerate without requiring explicit knowledge of its device ID. > > > > > > > > The primary use case is USB BT variants of combo chips that share the > > > > same PCIe device ID as their UART counterpart (e.g. WCN7851 NCM865 USB, > > > > sub 0x3378, vs NCM865A UART, sub 0x337c): no UART serdev is needed, but > > > > W_DISABLE2# must be deasserted so the USB BT device can enumerate. > > > > > > Instead of forcibly toggling it, would it be more sensible to tie pwrseq > > > into the USB too? The onboard-usb-dev implements the same idea (of > > > powering up the USB device), but it predates pwrseq. > > > > > > -- > > > With best wishes > > > Dmitry > > > > > > > Hi Dmitry, > > > > There is a patch series from Chen-Yu Tsai that appears to implement what > > you suggested: > > > > [PATCH v4 00/14] arm64: mediatek: Add M.2 E-key slot on Chromebooks > > https://lore.kernel.org/all/20260709095726.704448-1-wenst@chromium.org/ > > > > We have been testing this on the Qualcomm Hamoa IoT EVK with both UART BT > > and USB BT M.2 cards. Is this the direction you had in mind? > > > > IMO, we should move towards Chen's series. > > - Mani Agreed. While testing Chen-Yu's v4 on the Qualcomm Hamoa IoT EVK with a board that needs to support both USB and UART BT cards, we found that the USB hub holds a reference to the "usb" pwrseq target permanently (acquired in hub_activate() and never released). When the UART BT driver later calls pwrseq_power_off(), the bt_unit enable_count only drops to 1 and bt_disable() is never invoked, leaving W_DISABLE2# deasserted. This prevents the BT chip from being properly reset, causing the next btmgmt power on to fail. This issue is addressed in v5 Patch 14 by splitting the Bluetooth pwrseq unit into independent uart and usb units, each with their own reference count: [PATCH v5 00/16] arm64: mediatek: Add M.2 E-key slot on Chromebooks https://lore.kernel.org/all/20260715085348.3457359-1-wenst@chromium.org/ The series still needs review from you and other maintainers. -- Best Regards, Wei Deng