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AHgh+RpoIK1aMnblv3uPm9WK8Svri9SvSd4+ecSJ7jv+/OkO6MZiXwFuW4/4dtvVU+fn0ILXbGmTYb68aYRy5gc=@vger.kernel.org X-Gm-Message-State: AOJu0Yw9syZ7RLh/YY0t0Xunm/Is5YGGKR9qZH2R/yafwOeJG/YRBqfO pK3yGTunOtFLyN150xGDJzrS40mrwIdZSxL1sqo8WflXpcUU45clcEK3T5oY3BgWrx68cZun5H3 oR4SI1O06otgXkw== X-Received: from wrrg11.prod.google.com ([2002:adf:fc8b:0:b0:47f:4e4d:2531]) (user=smostafa job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6000:310d:b0:474:83d4:9916 with SMTP id ffacd0b85a97d-47f4885698emr7936900f8f.17.1784116778676; Wed, 15 Jul 2026 04:59:38 -0700 (PDT) Date: Wed, 15 Jul 2026 11:59:01 +0000 In-Reply-To: <20260715115906.2664882-1-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260715115906.2664882-1-smostafa@google.com> X-Mailer: git-send-email 2.55.0.141.g00534a21ce-goog Message-ID: <20260715115906.2664882-21-smostafa@google.com> Subject: [PATCH v7 20/24] iommu/arm-smmu-v3-kvm: Emulate GBPA From: Mostafa Saleh To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jgg@ziepe.ca, mark.rutland@arm.com, qperret@google.com, tabba@google.com, vdonnefort@google.com, sebastianene@google.com, keirf@google.com, Mostafa Saleh Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable The last bit of emulation is GBPA. it must be always set to ABORT, as when the SMMU is disabled it=E2=80=99s not allowed for the host to bypas= s the SMMU. That's is done by setting the GBPA to ABORT at init time, and host writes are always ignored and host reads always return ABORT. Signed-off-by: Mostafa Saleh --- .../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 32 +++++++++++++++++-- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iom= mu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c index 11de73640a6f..45dbab1b18ad 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c @@ -139,6 +139,22 @@ static bool smmu_cmdq_has_space(struct arm_smmu_queue = *cmdq, u32 n) return queue_has_space(llq, n); } =20 +static int smmu_abort_gbpa(struct hyp_arm_smmu_v3_device *smmu) +{ + int ret; + u32 reg; + + ret =3D smmu_wait(false, + (readl_relaxed(smmu->base + ARM_SMMU_GBPA) & GBPA_UPDATE) =3D=3D 0); + if (ret) + return ret; + + reg =3D readl_relaxed(smmu->base + ARM_SMMU_GBPA); + writel_relaxed(GBPA_UPDATE | GBPA_ABORT | reg, smmu->base + ARM_SMMU_GBPA= ); + return smmu_wait(false, + (readl_relaxed(smmu->base + ARM_SMMU_GBPA) & GBPA_UPDATE) =3D=3D 0); +} + static bool smmu_cmdq_full(struct arm_smmu_queue *cmdq) { struct arm_smmu_ll_queue *llq =3D &cmdq->llq; @@ -450,6 +466,10 @@ static int smmu_init_device(struct hyp_arm_smmu_v3_dev= ice *smmu) if (ret) goto out_ret; =20 + ret =3D smmu_abort_gbpa(smmu); + if (ret) + goto out_ret; + return 0; =20 out_ret: @@ -763,10 +783,16 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_d= evice *smmu, val =3D smmu->host_ste_cfg; goto out_update_regs; } - /* Passthrough the register access for bisectiblity, handled later */ case ARM_SMMU_GBPA: - mask =3D read_write; - break; + if (len !=3D sizeof(u32)) + break; + + /* Ignore write, always read to abort. */ + if (!is_write) { + val =3D GBPA_ABORT; + goto out_update_regs; + } + goto out_ret; case ARM_SMMU_CR0: if (len !=3D sizeof(u32)) break; --=20 2.55.0.141.g00534a21ce-goog