From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E739481A94; Wed, 15 Jul 2026 15:32:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784129527; cv=none; b=dzTQBptZ7sici+NFuJJzVW9XWP6RmxQV7wMAa4UmzBw4qyPV6RjEIfkw8JSZ0iapHPLRM+UibZW5w5tW9LJ4IRxgZw6Aon5r8qoF36Gcrjxl5eRMmy04rYMoawvb7nx4lLo0CBks6cfbVOBQt72WJ1jZWEjIuVk2brsSMMOkD2Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784129527; c=relaxed/simple; bh=Lshi9sQ25US/w7mSDhEzkx95l4ZmEu9mkyA3zF2Uj9A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ErLDq6wuE4Gf8Rw5yVpHIWATVC7/VSfRtmSa43mZhUS90RKN2t+75FaZnP2w1Z2L9m+q8N8fXtSPLPVg2BEO4x9F9os+5QT49MD5UVCwKTSS1G62kVZPb3gmjyolXxWoGoxjv/yp+XhTJ5QIt7eTZ5kpCs2NoraVhH17fvCRQgg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Dgbcomzv; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Dgbcomzv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1784129526; x=1815665526; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Lshi9sQ25US/w7mSDhEzkx95l4ZmEu9mkyA3zF2Uj9A=; b=DgbcomzvW/sysmTMx0C372k1P3LMv52ANbcWZVrsXye/eiDxSdV1S4V8 7wOoWxjoBvX/4zxWOFunr8gDkY+zvqtuAww5DGFwcT1AQqm3OlU13ebiD ImLktv0kqgc5cbOiZ6PuDY8vm21RJkamTsWANtBn1VUBo6R8zBCMV/yU6 FGBdKdiXGqoi0U2hXChAipYotDehHhrf4fVD8va0NrhBsIt5SViiGGwHT n4VVmq+dsSLENXcHhwHi7WqATm8TXdXTCXIDTwsEeYU6KT22ERJ1qeac5 FWHgXNnNbNUl78Lq2HChboCzcVPn8+S/kC4sL91wc5bxXzhjo9okVvFiO w==; X-CSE-ConnectionGUID: yuIv5Ii1R2GkS4Il3Y38WQ== X-CSE-MsgGUID: aN69luQaQ0G/yLI0nN4YEg== X-IronPort-AV: E=McAfee;i="6800,10657,11847"; a="84654767" X-IronPort-AV: E=Sophos;i="6.25,165,1779174000"; d="scan'208";a="84654767" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jul 2026 08:32:06 -0700 X-CSE-ConnectionGUID: nVExGMkHTfiG63zhnFONqw== X-CSE-MsgGUID: x8MZNGt4SS+r5MdIzktVBg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,165,1779174000"; d="scan'208";a="255093498" Received: from black.igk.intel.com ([10.91.253.5]) by orviesa010.jf.intel.com with ESMTP; 15 Jul 2026 08:32:04 -0700 From: Heikki Krogerus To: Matthew Brost , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Raag Jadav , Mika Westerberg , Andy Shevchenko Cc: Andi Shyti , Ramesh Babu B , "Michael J. Ruhl" , linux-kernel@vger.kernel.org, intel-xe@lists.freedesktop.org, stable@vger.kernel.org Subject: [PATCH v5 3/3] drm/xe/i2c: Keep the i2c controller always enabled Date: Wed, 15 Jul 2026 17:31:53 +0200 Message-ID: <20260715153153.1243751-4-heikki.krogerus@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260715153153.1243751-1-heikki.krogerus@linux.intel.com> References: <20260715153153.1243751-1-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Some platforms make an assumption that the i2c controller's enabled state indicates also the power state of the controller. This can create a problem when the controller is in disabled state, because the hardware may assume incorrectly that it is then also in low-power state. To fix this, the controller is kept enabled by taking over the IC_ENABLE register. The controller has to be disabled when the configuration is updated and when the target address or the slave address are assigned, so disabling it when IC_CON, IC_TAR or IC_SAR registers are programmed, and then re-enabling it again. Fixes: f0e53aadd702 ("drm/xe: Support for I2C attached MCUs") Cc: stable@vger.kernel.org Signed-off-by: Heikki Krogerus --- drivers/gpu/drm/xe/xe_i2c.c | 55 +++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/xe/xe_i2c.h | 1 + 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_i2c.c b/drivers/gpu/drm/xe/xe_i2c.c index 731e166e1f83d..4c26f8fdbfe83 100644 --- a/drivers/gpu/drm/xe/xe_i2c.c +++ b/drivers/gpu/drm/xe/xe_i2c.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -214,11 +215,40 @@ void xe_i2c_irq_postinstall(struct xe_device *xe) xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, PCI_COMMAND_INTX_DISABLE, 0); } +/* See "Disabling DW_apb_i2c" in the DesignWare DW_abp_i2c databook. */ +static void xe_i2c_disable(struct xe_i2c *i2c) +{ + int timeout = 100; + u32 status; + + xe_mmio_rmw32(i2c->mmio, I2C_REG(DW_IC_ENABLE), DW_IC_ENABLE_ENABLE, 0); + + do { + status = xe_mmio_read32(i2c->mmio, I2C_REG(DW_IC_ENABLE_STATUS)); + if (!(status & DW_IC_ENABLE_ENABLE)) + return; + /* Can't sleep here. */ + udelay(25); + } while (timeout--); + + dev_warn(i2c->drm_dev, "timeout in disabling i2c adapter\n"); +} + static int xe_i2c_read(void *context, unsigned int reg, unsigned int *val) { struct xe_i2c *i2c = context; - *val = xe_mmio_read32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET)); + *val = xe_mmio_read32(i2c->mmio, I2C_REG(reg)); + + switch (reg) { + case DW_IC_ENABLE: + case DW_IC_ENABLE_STATUS: + FIELD_MODIFY(DW_IC_ENABLE_ENABLE, val, + i2c->ic_enable & DW_IC_ENABLE_ENABLE); + break; + default: + break; + } return 0; } @@ -227,7 +257,28 @@ static int xe_i2c_write(void *context, unsigned int reg, unsigned int val) { struct xe_i2c *i2c = context; - xe_mmio_write32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET), val); + switch (reg) { + case DW_IC_CON: + case DW_IC_TAR: + case DW_IC_SAR: + /* Disable the controller. */ + xe_i2c_disable(i2c); + + /* Write the register. */ + xe_mmio_write32(i2c->mmio, I2C_REG(reg), val); + + /* Enable the controller. */ + xe_mmio_rmw32(i2c->mmio, I2C_REG(DW_IC_ENABLE), 0, DW_IC_ENABLE_ENABLE); + break; + case DW_IC_ENABLE: + i2c->ic_enable = val; + /* Other fields can be updated except the enable bit. */ + val |= DW_IC_ENABLE_ENABLE; + fallthrough; + default: + xe_mmio_write32(i2c->mmio, I2C_REG(reg), val); + break; + } return 0; } diff --git a/drivers/gpu/drm/xe/xe_i2c.h b/drivers/gpu/drm/xe/xe_i2c.h index b200966b00484..d63adacfefe71 100644 --- a/drivers/gpu/drm/xe/xe_i2c.h +++ b/drivers/gpu/drm/xe/xe_i2c.h @@ -37,6 +37,7 @@ struct xe_i2c { struct platform_device *pdev; struct i2c_adapter *adapter; struct i2c_client *client[XE_I2C_MAX_CLIENTS]; + unsigned int ic_enable; struct notifier_block bus_notifier; struct work_struct work; -- 2.50.1