From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EE1D3845A2 for ; Thu, 16 Jul 2026 05:28:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784179685; cv=none; b=Y+3eGZsC+5j7k7Aso2lw0USWMvDHvs4lOynMJu3GtCsjdQZKyhMnRUkIrjVorJAnGVjoKNUG+jzJxAO0sOkodT5nrNTv3RtyiMXRSuJuaBtBlFnIsNRrb6lIZ//G7Rp84uz6g2blKhHxUZv86oseQz0guTqb8XW+JDHuhDdEO/k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784179685; c=relaxed/simple; bh=FJCOkr82uBlHtDHrHTjLZhw8Ri5FjduiBo/WDahh6Sg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=c0iFs5PxRlzzTQUAhdHr2GRkiHtDlGLuEJNebnH3LrZGGJbKFDQ0pPPK1G1Ic+ojjmUXToPn3JucFjRPVF7TR86rm8nY16wq5ISc2h9gkViyDHXZqlUlmItwiiB8juYdBIEAkkKUxRXQOk6tzNaGJZVO6eexnm/KsbX7CKdGZuw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=ZIr5OAkz; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=dWGy0I2B; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="ZIr5OAkz"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="dWGy0I2B" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66G3wMdw1753938 for ; Thu, 16 Jul 2026 05:28:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= R6h9FcF9DDa6d36d3YHHrMo5TXJSy+ELkvqqZiE+R+s=; b=ZIr5OAkzYCykFMPV zTCvT4MhJoiIPksmp7j7irsvfxejURdJbhAosPVdY/sX+wrZcWBobiPXezbcmB/J EZeS+xuHntUIRw5jl/tLjkXik2UnPVZgYkqLf0hDG0+Gu9LQSfwQsrciRqylxvLr xEP5jmmlWgL1cWSVV4eqS4Q75LFugwSvsqo9bFGSzfsM6/5jZ6fZtC4DpI9r+ooF xcIhyYlCQe7EmFUS2nGkJv2v0+Syqy7F3bNnv2KI6rgIU5H5XG1S+G1yQyY6zwyi MHjxCU2JWPB6TZIuBF6R+VrSp6ljUALCKCyzYh4r0ZEJNrqPn2kOoekA2E22yFl7 +NW2aQ== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fe855c3x9-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 16 Jul 2026 05:28:02 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-c88aab7c1fcso14859365a12.3 for ; Wed, 15 Jul 2026 22:28:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784179682; x=1784784482; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=R6h9FcF9DDa6d36d3YHHrMo5TXJSy+ELkvqqZiE+R+s=; b=dWGy0I2BOLOV3t+mh5Sab27rk7D96seozrYFqlp42BWUIR0d2i8shdB4f0t7W6LUXZ TMRkBYsR5plOlm6+p+U7JjNtF2B5HyCZw6RLmHz+J8o108c7VGBofKZmmTn6xOJHRuFD fdAGr6OdnRuuPC4QTMsxGfc4WIKNqAzst0Zt0+5Qq35PlphE8LG7MP7F1ZmU80af7zIf MXR07D+lGQSeLD+J6Pzo1d0c47oZ3XTbizv9PYYv+xnJnbJfzxC5WcEhgsx1hqGz5Uor 19MEpJsuIE16yVrP5TntyzAq6aHTG6FmBe56b3e2uFF5wcXO7Rp2ahTt64oGwJtuYe4J wBww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784179682; x=1784784482; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=R6h9FcF9DDa6d36d3YHHrMo5TXJSy+ELkvqqZiE+R+s=; b=sYuLimTOskPa3+RPg9w6Ztq/+rNw0SLmJaYw1YAlsPYEzaHR/PfNT5Rg23oG9JASsK pkZYt3GuU4QLJrg6O/WOwasRZubZQiDed2xnvjVgZpLIVqjm+auiTlWk0t9WCb6p0HqH Iya7EZcL9KyNLw/pCyK4y4PdRE3o0NrGxhH/2DVx+Cf+/ZAPORinfyL9UKkTkqZZJpqd jEamSZiT8Z4f8RcQZAL8j7nTCATV4ZBcnW4HHrBcznFMRAoS5L5RhxtOSc/p+FDhDgL/ TkUNGiqpDIXjes+YnMAyKpMvbVeN+qtEpdvf8Fe/YDbV/jsXKDoM93KIGKaW6riB+Hcz lGTQ== X-Forwarded-Encrypted: i=1; AHgh+RrOzZ8n8bXRPZc2a671hHkHZyXpd8388dOiqqf3aGO82I9vGg0WjtRnP/gbxyBTPnqByz6T+I1xALiHBj0=@vger.kernel.org X-Gm-Message-State: AOJu0YyHpfd6BJqtySmqi/JYHuWwvlj97jnKCPAoThyaAbcq/YRBFyz+ GMmSSTUgtjYgnPKXdmZHEh3lBO6Na7xyh4PYHl4eVvJCEAZtKcB7lAXUbZ+HTTA10HEG3CFWg22 a2wo9klZGHRxXVYbUHIxP7PPqAOdH812hpufiDWccse+cWfyrLQMOWXHTJC8cI2CVY/MBhTV8lE 8= X-Gm-Gg: AfdE7cmWOAXYA39A2E9D6EWQVz8L192M3C+6xxvFK4MvpAYM52E24C1CfQVLf1iP9ge 2SbmWKdha7pZxTjRbShKi9vw4zzf4vePKHRGqpcW+Y4KjjSMLYt4+qEt9sapKlVP4KPhb6D16NF IZsNgso4LkCiJX+N/CQCsFtj4kdOOtJ/Cw6bJ3KHznJppuYtljOZDJ7FsPj5BIuvUInGsBPGjie 7eqx4JEKT+Z4wtVhoxU/oHy/YK6bknIpH0rHDmTMb8i9lIdaNA61mElVOnXYu8Q7+vYyc8piIBm y8wNL+GnaFS14hkl2Sh1rg6m6kLgdJA1iMLvV0/gt9fd7AERrPrRIHlOblH6FO4ndxKmT57C65J rRZrSFpTUkSXD0iNeF6Y9a3YLrqay43fahvatDzaepNff8WATYUAwUeO5WVuU7XWlJcgTununTQ yBEdYNeysIKik= X-Received: by 2002:a05:6a20:93a1:b0:3c3:8f0f:b6a0 with SMTP id adf61e73a8af0-3c38f0fbae6mr1214412637.49.1784179681541; Wed, 15 Jul 2026 22:28:01 -0700 (PDT) X-Received: by 2002:a05:6a20:93a1:b0:3c3:8f0f:b6a0 with SMTP id adf61e73a8af0-3c38f0fbae6mr1214388637.49.1784179681048; Wed, 15 Jul 2026 22:28:01 -0700 (PDT) Received: from hu-mdalam-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3140e53349dsm7795812eec.7.2026.07.15.22.27.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 22:28:00 -0700 (PDT) From: Md Sadre Alam Date: Thu, 16 Jul 2026 10:57:46 +0530 Subject: [PATCH 2/3] spi: spi-qpic-snand: add quad mode support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260716-quad-v1-2-636f74da17e1@qti.qualcomm.com> References: <20260716-quad-v1-0-636f74da17e1@qti.qualcomm.com> In-Reply-To: <20260716-quad-v1-0-636f74da17e1@qti.qualcomm.com> To: Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Md Sadre Alam , Md Sadre Alam X-Mailer: b4 0.14.3 X-Proofpoint-GUID: qeJaLq7dL21PaKYqVIhWZb2Lu35pDWmC X-Authority-Analysis: v=2.4 cv=KOlqylFo c=1 sm=1 tr=0 ts=6a586be2 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=LCgf8a1I7HAfrTGDgyUA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE2MDA1MyBTYWx0ZWRfX7pPgnkGtnytG Eb0PItj5lApjJ5SPbEYWbNjy63/+GgWQ/s4g5kidYuHH54MmDARqJBotz/LeEzaDynq1VISCdrR U+CI1sbkSTJx08bkfiqjX0vMldknP/PfVyVrJ4v/2dSUyzWYhgjdpChuBXaRn03mwO5E/L8PG6W q4GYyfi+l/MNDoN3LY4L2J84m5T2L36Kg3YiqLisV1WMV30Mt13YiR1hyglMqKCv7/fimPfYksn FdhrpSuqGjV0SIZ3hMpyEyS6OtJqRn3j2E4mgDdyxsxh6nw+naaXPNIWcSywOKI4SjE9lz8Po/7 Hj2EuGFQ96jOSpPhXFzZl9XeEYbYRB81AmMQqoSpMQ7eU2SoOTquc7niQqG28wzumaGbThwKIzS dbfJC5cwOGHcZb9JB6VKd4TSIhOO9pcvQIcUC+ANcpjn8MrohvoNlz6NmTMGkSQ6vfMoQBuiFG7 +7NaegcYCLaVEvCMh+w== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE2MDA1MyBTYWx0ZWRfX4fv7bv/NJIlw HSUT5wS4n3xwrkpdL7fvQIAtMCGxbBVgezRuyk9pmkhTc6TrxGUXoFucTGfG8yBbB2QVzwCkmc3 kublPwZokQ3vZNNNGUy4DEgosFgvk+c= X-Proofpoint-ORIG-GUID: qeJaLq7dL21PaKYqVIhWZb2Lu35pDWmC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-16_02,2026-07-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 impostorscore=0 malwarescore=0 spamscore=0 clxscore=1015 priorityscore=1501 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607160053 Add support for quad (x4) transfer mode in the QPIC SPI NAND driver. The controller supports both single (x1) and quad (x4) SPI transfers, but the driver currently operates only in x1 mode. Track the QUAD enable state from the device configuration register (0xB0) and switch the data transfer width accordingly. When the core enables quad mode, use x4 transfers for read and program operations to improve throughput. Introduce a quad_mode flag in struct qpic_spi_nand to cache the current device state. The flag is updated based on GET_FEATURE responses from the configuration register. Signed-off-by: Md Sadre Alam --- drivers/spi/spi-qpic-snand.c | 67 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 58 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c index b96b6d149ca5..5c077f7023f1 100644 --- a/drivers/spi/spi-qpic-snand.c +++ b/drivers/spi/spi-qpic-snand.c @@ -46,14 +46,19 @@ #define SPINAND_RESET 0xff #define SPINAND_READID 0x9f +#define SPINAND_FEATURE_ADDR 0xb0 #define SPINAND_GET_FEATURE 0x0f #define SPINAND_SET_FEATURE 0x1f +#define SPINAND_READ_CACHE 0x0b #define SPINAND_READ 0x13 +#define SPINAND_READ_QUAD 0xeb #define SPINAND_ERASE 0xd8 #define SPINAND_WRITE_EN 0x06 #define SPINAND_PROGRAM_EXECUTE 0x10 #define SPINAND_PROGRAM_LOAD 0x84 +#define SPINAND_PROGRAM_LOAD_QUAD 0x34 +#define QUAD_WIDTH 0x4 #define ACC_FEATURE 0xe #define BAD_BLOCK_MARKER_SIZE 0x2 #define OOB_BUF_SIZE 128 @@ -114,6 +119,7 @@ struct qpic_spi_nand { bool oob_rw; bool page_rw; bool raw_rw; + bool quad_mode; }; static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc, @@ -991,8 +997,15 @@ static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc, return qcom_spi_check_error(snandc); } -static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, u32 *cmd) +static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, + const struct spi_mem_op *op, u32 *cmd) { + u32 opcode = op->cmd.opcode; + u32 transfer_mode = SPI_TRANSFER_MODE_x1; + + if (snandc->qspi->quad_mode && op->data.buswidth == QUAD_WIDTH) + transfer_mode = SPI_TRANSFER_MODE_x4; + switch (opcode) { case SPINAND_RESET: *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE); @@ -1008,11 +1021,13 @@ static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, QPIC_SET_FEATURE); break; case SPINAND_READ: + case SPINAND_READ_QUAD: + case SPINAND_READ_CACHE: if (snandc->qspi->raw_rw) { - *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | + *cmd = (PAGE_ACC | LAST_PAGE | transfer_mode | SPI_WP | SPI_HOLD | OP_PAGE_READ); } else { - *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | + *cmd = (PAGE_ACC | LAST_PAGE | transfer_mode | SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC); } @@ -1025,12 +1040,16 @@ static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, *cmd = SPINAND_WRITE_EN; break; case SPINAND_PROGRAM_EXECUTE: - *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | - SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE); + if (snandc->qspi->quad_mode) + *cmd = (PAGE_ACC | LAST_PAGE | transfer_mode | + SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE); break; case SPINAND_PROGRAM_LOAD: *cmd = SPINAND_PROGRAM_LOAD; break; + case SPINAND_PROGRAM_LOAD_QUAD: + *cmd = SPINAND_PROGRAM_LOAD_QUAD; + break; default: dev_err(snandc->dev, "Opcode not supported: %u\n", opcode); return -EOPNOTSUPP; @@ -1042,6 +1061,15 @@ static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, static int qcom_spi_read_page(struct qcom_nand_controller *snandc, const struct spi_mem_op *op) { + int ret; + u32 cmd; + /* Call mapping once again to update the quad mode based on + * buswidth + */ + ret = qcom_spi_cmd_mapping(snandc, op, &cmd); + if (ret < 0) + return ret; + if (snandc->qspi->page_rw && snandc->qspi->raw_rw) return qcom_spi_read_page_raw(snandc, op); @@ -1309,11 +1337,12 @@ static int qcom_spi_write_page(struct qcom_nand_controller *snandc, int ret; u32 cmd; - ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); + ret = qcom_spi_cmd_mapping(snandc, op, &cmd); if (ret < 0) return ret; - if (op->cmd.opcode == SPINAND_PROGRAM_LOAD) + if (op->cmd.opcode == SPINAND_PROGRAM_LOAD || + op->cmd.opcode == SPINAND_PROGRAM_LOAD_QUAD) snandc->qspi->data_buf = (u8 *)op->data.buf.out; return 0; @@ -1325,7 +1354,7 @@ static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc, u32 cmd; int ret, opcode; - ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); + ret = qcom_spi_cmd_mapping(snandc, op, &cmd); if (ret < 0) return ret; @@ -1430,6 +1459,22 @@ static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struct spi_ val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf); val >>= 8; memcpy(op->data.buf.in, &val, snandc->buf_count); + + /* + * Track QUAD mode state from configuration register. + * When core layer reads register 0xB0 (CFG), check if + * QUAD enable bit (bit 0) is set and update our state + * accordingly for future READ/WRITE operations. + */ + if (op->addr.val == SPINAND_FEATURE_ADDR) { + bool quad_enabled = !!((u8)val & BIT(0)); + + if (snandc->qspi->quad_mode != quad_enabled) { + snandc->qspi->quad_mode = quad_enabled; + dev_info(snandc->dev, "SPI NAND QUAD mode: %s\n", + quad_enabled ? "enabled" : "disabled"); + } + } } return 0; @@ -1470,7 +1515,8 @@ static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *o return ((!op->addr.nbytes || op->addr.buswidth == 1) && (!op->dummy.nbytes || op->dummy.buswidth == 1) && - (!op->data.nbytes || op->data.buswidth == 1)); + (!op->data.nbytes || op->data.buswidth == 1 || + op->data.buswidth == 4)); } static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) @@ -1521,6 +1567,9 @@ static int qcom_spi_probe(struct platform_device *pdev) if (!qspi) return -ENOMEM; + /* Initialize QUAD mode state */ + qspi->quad_mode = false; + ctlr = __devm_spi_alloc_controller(dev, sizeof(*snandc), false); if (!ctlr) return -ENOMEM; -- 2.34.1