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Thu, 16 Jul 2026 07:27:37 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1wkN3p-00000002WW2-0fBf; Thu, 16 Jul 2026 11:27:37 -0300 Date: Thu, 16 Jul 2026 11:27:37 -0300 From: Jason Gunthorpe To: Lu Baolu Cc: Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH 1/1] iommu/vt-d: Disallow SVA if page walk is not coherent Message-ID: <20260716142737.GC210048@ziepe.ca> References: <20260716053554.1642374-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260716053554.1642374-1-baolu.lu@linux.intel.com> On Thu, Jul 16, 2026 at 01:35:53PM +0800, Lu Baolu wrote: > Hardware implementations report Scalable-Mode Page-walk Coherency Support > via the SMPWCS field in the extended capability register. If the hardware > does not support page-walk coherency, a clflush is required every time > the page table entries (which are walked by the IOMMU hardware) are > updated. > > In the SVA case, page tables are managed by the CPU mm core, not by the > IOMMU driver. Because the IOMMU driver has no way of knowing whether the > CPU page table management code has ensured coherency via clflush, the > driver must deny SVA if the hardware does not support coherent paging. > > Fixes: ff3dc6521f78 ("iommu/vt-d: Fix CPU and IOMMU SVM feature matching checks") > Cc: stable@vger.kernel.org > Signed-off-by: Lu Baolu > --- > drivers/iommu/intel/svm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Jason Gunthorpe Jason