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Fri, 17 Jul 2026 06:20:41 -0700 (PDT) From: Fernando Rimoli To: Daniel Scally , Sakari Ailus , linux-media@vger.kernel.org Cc: Mauro Carvalho Chehab , Arsalan Naeem , linux-kernel@vger.kernel.org, Fernando Rimoli Subject: [PATCH v2 0/3] media: Enable the OV5693 front camera on IPU6 Surface devices Date: Fri, 17 Jul 2026 15:20:18 +0200 Message-ID: <20260717132021.18034-1-fernandorimoli11@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260708213633.18392-1-fernandorimoli11@gmail.com> References: <20260708213633.18392-1-fernandorimoli11@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Apologies for the slow turnaround on v2, I wanted to properly characterise the MIPI_CTRL00 register before answering, and I was coordinating with Arsalan Naeem, who originally found the register write (linux-surface PR#2171); the third patch is co-developed with him. This enables the OV5693 front camera on Intel IPU6 Surface devices such as the Microsoft Surface Pro 9. Three independent pieces are needed on a stock kernel: 1/3 ov5693: add the "OVTI5693" ACPI HID so the i2c core binds the driver (these devices enumerate the sensor as OVTI5693, not INT33BE). 2/3 ipu-bridge: add the same HID so the bridge builds the sensor's fwnode graph. 3/3 ov5693: gate the MIPI clock lane, which the IPU6 CSI-2 receiver needs in order to lock (this is the register write from PR#2171). On the MIPI_CTRL00 value, in reply to Sakari's question on v1: I swept the register on a Surface Pro 9 (IPU6) with read-back. The power-on default reads 0x00. Every value with bit 5 (clock-lane gate) set streams (300/300 frames, steady ~28 fps); every value with bit 5 clear, including 0x00 and 0x04 (LP11-idle alone), fails with "stream stop time out" and no frames. So bit 5 is the decisive bit for IPU6, and 0x04 alone is not enough. Bit 5 is not an IPU6-specific hack: ov5640, ov5647 and ov5648 all gate the clock lane on every platform. Patch 3 sets bit 5 plus bit 2 (LP11-idle, i.e. 0x24, matching ov5640's value); I have only been able to test this on IPU6, not on IPU3 (CIO2) or Rockchip, so I have kept it to the conventional OV-family bits rather than the vendor's 0x2d (which also sets bit 3 and an undocumented bit 0). Patches 1-2 are independent of patch 3 and useful on their own for enumeration; patch 1 carries Dan Scally's Reviewed-by from v1. Changes since v1 [1]: - Split the single v1 patch into the two HID patches (1/3, 2/3), as requested by Sakari. - Added patch 3/3, the MIPI clock-lane gate, co-developed with Arsalan Naeem, with the characterisation above answering Sakari's v1 question. - Carried Daniel Scally's Reviewed-by on patch 1/3. - Used named bit macros instead of a bare register value. [1] https://lore.kernel.org/linux-media/20260708213633.18392-1-fernandorimoli11@gmail.com/ Fernando Rimoli (3): media: i2c: ov5693: Add OVTI5693 ACPI HID media: ipu-bridge: Add OVTI5693 to the list of supported sensors media: i2c: ov5693: Gate the MIPI clock lane for IPU6 drivers/media/i2c/ov5693.c | 21 +++++++++++++++++++++ drivers/media/pci/intel/ipu-bridge.c | 2 ++ 2 files changed, 23 insertions(+) -- 2.43.0