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Fri, 17 Jul 2026 06:20:44 -0700 (PDT) From: Fernando Rimoli To: Daniel Scally , Sakari Ailus , linux-media@vger.kernel.org Cc: Mauro Carvalho Chehab , Arsalan Naeem , linux-kernel@vger.kernel.org, Fernando Rimoli Subject: [PATCH v2 3/3] media: i2c: ov5693: Gate the MIPI clock lane for IPU6 Date: Fri, 17 Jul 2026 15:20:21 +0200 Message-ID: <20260717132021.18034-4-fernandorimoli11@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260717132021.18034-1-fernandorimoli11@gmail.com> References: <20260708213633.18392-1-fernandorimoli11@gmail.com> <20260717132021.18034-1-fernandorimoli11@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The ov5693 never programs MIPI_CTRL00 (0x4800), leaving it at its 0x00 power-on default (free-running MIPI clock). The IPU3 CSI-2 receiver tolerates this, but the IPU6 receiver (e.g. on Microsoft Surface Pro 8/9 and Surface Go 4) fails to lock onto the link, so the sensor streams but capture times out with "stream stop time out" and no frames arrive. Gating the clock lane when idle (MIPI_CTRL00 bit 5) makes the IPU6 receiver lock. This was determined by sweeping the register on a Surface Pro 9 (IPU6): every value with bit 5 set streams (300/300 frames, steady 28 fps), every value with bit 5 clear fails with the CSI-2 timeout; register read-back confirmed the power-on default is 0x00. Bit 5 is the conventional OmniVision clock-lane-gate setting (ov5640, ov5647 and ov5648 all set it on every platform), so it is not an IPU6-specific hack. Bit 2 (bus idle in LP11) is set as well, matching ov5640's value; this was tested only on IPU6. Link: https://github.com/linux-surface/linux-surface/pull/2171 Co-developed-by: Arsalan Naeem Signed-off-by: Arsalan Naeem Signed-off-by: Fernando Rimoli --- drivers/media/i2c/ov5693.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/media/i2c/ov5693.c b/drivers/media/i2c/ov5693.c index 02236f3db..d1b38348e 100644 --- a/drivers/media/i2c/ov5693.c +++ b/drivers/media/i2c/ov5693.c @@ -35,6 +35,12 @@ #define OV5693_STOP_STREAMING 0x00 #define OV5693_SW_RESET 0x01 +/* MIPI transmitter control */ +#define OV5693_MIPI_CTRL00_REG CCI_REG8(0x4800) +/* bit 5: gate the clock lane when idle; bit 2: keep the bus in LP11 when idle */ +#define OV5693_MIPI_CTRL00_CLOCK_LANE_GATE BIT(5) +#define OV5693_MIPI_CTRL00_BUS_IDLE BIT(2) + #define OV5693_REG_CHIP_ID CCI_REG16(0x300a) /* Yes, this is right. The datasheet for the OV5693 gives its ID as 0x5690 */ #define OV5693_CHIP_ID 0x5690 @@ -611,6 +617,20 @@ static int ov5693_enable_streaming(struct ov5693_device *ov5693, bool enable) { int ret = 0; + /* + * Gate the MIPI clock lane when idle. The power-on default of + * MIPI_CTRL00 is 0x00 (free-running clock), which the IPU3 CSI-2 + * receiver tolerates but the IPU6 one does not: it fails to lock onto + * the link and capture times out. Gating the clock lane (bit 5) is + * required for IPU6 and is the conventional setting for OmniVision + * sensors (cf. ov5640, ov5647, ov5648); also keep the bus in LP11 when + * idle (bit 2). Harmless on IPU3. + */ + if (enable) + cci_write(ov5693->regmap, OV5693_MIPI_CTRL00_REG, + OV5693_MIPI_CTRL00_CLOCK_LANE_GATE | + OV5693_MIPI_CTRL00_BUS_IDLE, &ret); + cci_write(ov5693->regmap, OV5693_SW_STREAM_REG, enable ? OV5693_START_STREAMING : OV5693_STOP_STREAMING, &ret); -- 2.43.0