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[61.228.46.68]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84c2ad87f83sm1332576b3a.3.2026.07.17.08.46.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jul 2026 08:46:55 -0700 (PDT) From: Shih-Yuan Lee To: Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Shih-Yuan Lee Subject: [PATCH v3 0/2] spi: pxa2xx: MacBook8,1 quirk and LPSS S3 resume state fixes Date: Fri, 17 Jul 2026 23:46:44 +0800 Message-Id: <20260717154646.5854-1-fourdollars@debian.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260712162420.7453-1-fourdollars@debian.org> References: <20260712162420.7453-1-fourdollars@debian.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Mark, This patch series resolves two issues in the spi-pxa2xx host controller driver related to Intel LPSS SPI controllers. Patch 1 moves the forced PIO mode quirk for the Apple MacBook8,1 LPSS SPI controller from the client driver (applespi) to the host controller PCI glue driver (spi-pxa2xx-pci) where it belongs. It also fixes a runtime PM issue: when DMA is disabled, aggressive runtime clock gating causes PCIe Completion Timeouts on subsequent MMIO accesses. Patch 2 fixes S3 suspend/resume for Intel LPSS SPI controllers. The LPSS power domain is fully removed across S3, losing all private register state. Accessing MMIO on resume while the block is held in reset causes a PCIe Completion Timeout and a watchdog system reset. To fix this, we save the LPSS private registers in struct driver_data during suspend, de-assert resets first on resume, and restore the saved registers. Changes in v3: - Addressed feedback from upstream AI review regarding PM reference leaks, races in the shared interrupt handler, and teardown order: - Avoid PM reference leaks on probe bind/unbind cycle by keeping probe PM configuration symmetric. - Prevent userspace (PowerTOP, udev) from overriding runtime PM settings when DMA is disabled by holding a PM reference via pm_runtime_get_noresume() in pxa2xx_spi_probe() and dropping it in remove/error paths. - Check device status in the shared interrupt handler ssp_int() using pm_runtime_get_if_active() instead of pm_runtime_suspended(). If the device is suspending (RPM_SUSPENDING) or suspended, ssp_int() immediately returns IRQ_NONE to avoid reading unclocked MMIO registers during power transition. - Call synchronize_irq() in pxa2xx_spi_runtime_suspend() to wait for active handlers on the shared interrupt line to finish before disabling the clock. - Adjust the driver teardown order in pxa2xx_spi_remove() and probe error paths: always call free_irq() to unregister the handler before calling clk_disable_unprepare() to turn off the clock, preventing concurrent interrupts from reading registers while the clock is disabled. - On S3 suspend success path, return 0 directly without dropping the PM reference. This preserves the acquired PM reference across suspend. On S3 resume, release it via pm_runtime_put_autosuspend(), and ensure all error paths in resume (clock enable failure or spi_controller_resume failure) jump to out_put to correctly release the reference, preventing reference count underflow and leaks. - Avoid duplicate can-DMA pci_info() logging by checking the pre-computed enable_dma status in probe and passing a verbose flag to can_dma(). Changes in v2: - Addressed feedback from Mark Brown on the original v1 series. - Used drv_data->lpss_base together with relative offsets rather than hardcoding absolute MMIO offsets that vary between LPSS IP revisions. - Moved the register save block in suspend to after the controller is quiesced (after spi_controller_suspend() and pxa_ssp_disable()). - Store the context array lpss_priv_ctx[6] inside struct driver_data instead of struct pxa2xx_spi_controller. This keeps the changes entirely local to the core driver, preventing symbol version mismatches (disagrees about version of symbol) for other subsystem components (e.g., spi-pxa2xx-platform.ko). - Restrict the save/restore loop to the first 6 LPSS private registers (offsets 0x00 to 0x14). Offsets beyond 0x14 (except CS control at 0x18, which is re-initialised by lpss_ssp_setup()) are reserved/unimplemented on LPT platforms (such as MacBook8,1), and writing to them triggers a PCIe Completion Timeout causing a system freeze. - Added named constants for LPSS_PRIV_RESETS and the de-assert value. - Wrapped S3 suspend/resume with pm_runtime_resume_and_get() and pm_runtime_put_autosuspend() respectively. Link: https://bugzilla.kernel.org/show_bug.cgi?id=108331 Shih-Yuan Lee (2): spi: pxa2xx: disable DMA and fix runtime PM for Apple MacBook8,1 spi: pxa2xx: restore LPSS private register state on S3 resume drivers/spi/spi-pxa2xx-pci.c | 47 ++++++++++-- drivers/spi/spi-pxa2xx.c | 140 ++++++++++++++++++++++++++++------- drivers/spi/spi-pxa2xx.h | 1 + 3 files changed, 157 insertions(+), 31 deletions(-) -- 2.39.5