From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 998C3383985; Sun, 19 Jul 2026 23:11:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784502698; cv=none; b=dhqbtS4a4bgiwOT6mb6m5Fu4kJGTvWeyyiWRwfWjpcWwEo9d41JWvRtkbIUGKzv40+ofbcAJTAY8bfuXDAmU/47AT4P/PIqwBnYj6RpxFiHWrVpFuu3v2fDEgUl4ROn/oL4w61oYwe4nyCwT1U7Nz2uc62VsLQ+8J7LD5QlYkvQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784502698; c=relaxed/simple; bh=smeCg9dfluu2jVyRmyUbJ43Gu0kVuoH5Oy7fiw1EXQo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=E7yGXbKby/4EDh5815NZd8mSBh/6XzKf2xTfoS4Lo3E3arFwriPl78jIUn0aPREVho/kN2jS/aFlB/k4M7PXBqvFl12Vo6/1FI8UVGD5WMPIBUWTrB8BVu54at8sduOSFCTT6GPo/qZ9q4ruTmDG8nBymP+mMU12HfBT8r4mZNw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QXjNmfdf; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QXjNmfdf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3BC031F000E9; Sun, 19 Jul 2026 23:11:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784502697; bh=qUAiHFykeyeMsRtI4ws0Xq5TjSptXUqvEwAkGiCNvkk=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=QXjNmfdfgkaJSkKACm5jsdjjXy5ZCspvzkirk4wS2bJ6vY1WGL9qpeY/ERnlw0vJb eRyHdLeiSG7XA391xkzdQsaizXmFuJHmsZuuPujG5j0QjWGg/twaoWXe4PaJ7UOCz4 Zqihx1mbgDCDXu6BJOUCjV5+hI3hMD6/fDLPkYOoDVRz9l4xKzFBwOj7sojSYBn+2Z vxvkmcoLCYWoQT/QIxYPNgTL2Gb1QQ1Vvcoq+OmdoRLwjig1YShlybeu9HBvN23MbF s0gZqwvZnYufBo4pe74JFwMyLlbaEFQQvEkdsBcv8nlNMdVb3ctGP9htnBT5bhfcjI YNh5ZEogsRv7Q== From: Mark Brown Date: Mon, 20 Jul 2026 00:07:50 +0100 Subject: [PATCH v13 23/32] KVM: arm64: Flush register state on writes to SVCR.SM and SVCR.ZA Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260720-kvm-arm64-sme-v13-23-d9abd3ffa245@kernel.org> References: <20260720-kvm-arm64-sme-v13-0-d9abd3ffa245@kernel.org> In-Reply-To: <20260720-kvm-arm64-sme-v13-0-d9abd3ffa245@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=5357; i=broonie@kernel.org; h=from:subject:message-id; bh=smeCg9dfluu2jVyRmyUbJ43Gu0kVuoH5Oy7fiw1EXQo=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqXVk5wf74d/IyOURWeDScGlye099xAOyqga6nC rd0mqvnRgKJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCal1ZOQAKCRAk1otyXVSH 0LdgB/wKfySzR7bDqvc9GDdBMRSKvPtBCTyfrmOMokjcmeifSfGfqtB3qoU1UOQ9js9uxIWYF9m AJmx7XS8RWvEeOqnB8AflYFTIdQmjRuRzlX/qggd1pV4f/lroHAkgLcOXuxPr/sybWJQ1a6IKom 2V/XxQ2uLAmpucG/UKeOYLfJsWjpX6iNB6Un669hrTNJ5G9DgD9yp6WS8YcruiA8U+l29DOM3gu YWFd/yP/hwuCThBUVDSoV/1UjOM2+O+mqU/2jk4IHCUUrK0YLIWLOLk+YDDTS1VFgKULOx/kxqw CYUxRnoZw0mcryGPiEGCCqY38s8Wkp70wiz93ss/Y9qP0vmI X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Writes to the physical SVCR.SM and SVCR.ZA change the state of PSTATE.SM and PSTATE.ZA, causing other floating point state to reset. Emulate this behaviour for writes done via the KVM userspace ABI. Setting PSTATE.ZA to 1 causes ZA and ZT0 to be reset to 0, these are stored in sme_state. Setting PSTATE.ZA to 0 causes ZA and ZT0 to become inaccessible so no reset is needed. Any change in PSTATE.SM causes the V, Z, P, FFR and FPMR registers to be reset to 0 and FPSR to be reset to 0x800009f. Rather than introduce a requirement that the vector configuration be finalised before writing to SVCR we check for this before updating the SVE and SME specific state, when finalisation happens they will be allocated with an initial state of 0. Similarly in order to avoid ordering requirements between finalisation and writes to the ID registers we always allocate space for ZT0 if the hardware supports it, this is 512 bits per vCPU. The overwhelming majority of practical systems with SME are expected to want use SME2, there is very little practical reason to disable it other than for feature testing, and the additional complexity seems more likely to lead to bugs than deliver practical benefits. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 28 ++++++++++++++++++++++++++++ arch/arm64/include/asm/sysreg.h | 2 ++ arch/arm64/kvm/sys_regs.c | 30 +++++++++++++++++++++++++++++- 3 files changed, 59 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 6574c286f50f..cafc43776ac3 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1142,6 +1142,34 @@ struct kvm_vcpu_arch { #define vcpu_sve_state_size(vcpu) sve_state_size_from_vl(vcpu_sve_max_vl(vcpu)) +#define vcpu_sme_state(vcpu) (kern_hyp_va((vcpu)->arch.sme_state)) + +#define sme_state_size_from_vl(vl, sme2) ({ \ + size_t __size_ret; \ + unsigned int __vq; \ + \ + if (WARN_ON(!sve_vl_valid(vl))) { \ + __size_ret = 0; \ + } else { \ + __vq = sve_vq_from_vl(vl); \ + __size_ret = ZA_SIG_REGS_SIZE(__vq); \ + if (sme2) \ + __size_ret += ZT_SIG_REG_BYTES; \ + } \ + \ + __size_ret; \ +}) + +/* + * Always provide space for ZT0 to avoid ordering requirements with ID + * register writes and vector finalization. + */ +#define vcpu_sme_state_size(vcpu) ({ \ + unsigned long __vl; \ + __vl = (vcpu)->arch.max_vl[ARM64_VEC_SME]; \ + sme_state_size_from_vl(__vl, system_supports_sme2()); \ +}) + #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ KVM_GUESTDBG_USE_SW_BP | \ KVM_GUESTDBG_USE_HW | \ diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 4b96449e0ffa..b434320de1a7 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1108,6 +1108,8 @@ #define gicr_insn(insn) read_sysreg_s(GICV5_OP_GICR_##insn) #define gic_insn(v, insn) write_sysreg_s(v, GICV5_OP_GIC_##insn) +#define FPSR_RESET_VALUE 0x800009f + #ifdef __ASSEMBLER__ .macro mrs_s, rt, sreg diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 827502e3249a..f55a8d65cfc2 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1015,6 +1015,34 @@ static unsigned int hidden_visibility(const struct kvm_vcpu *vcpu, return REG_HIDDEN; } +static int set_svcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, + u64 val) +{ + u64 old = __vcpu_sys_reg(vcpu, rd->reg); + + if (val & SVCR_RES0) + return -EINVAL; + + if ((val & SVCR_ZA) && !(old & SVCR_ZA) && + kvm_arm_vcpu_vec_finalized(vcpu)) + memset(vcpu->arch.sme_state, 0, vcpu_sme_state_size(vcpu)); + + if ((val & SVCR_SM) != (old & SVCR_SM)) { + memset(vcpu->arch.ctxt.fp_regs.vregs, 0, + sizeof(vcpu->arch.ctxt.fp_regs.vregs)); + + if (kvm_arm_vcpu_vec_finalized(vcpu)) + memset(vcpu->arch.sve_state, 0, + vcpu_sve_state_size(vcpu)); + + __vcpu_assign_sys_reg(vcpu, FPMR, 0); + vcpu->arch.ctxt.fp_regs.fpsr = FPSR_RESET_VALUE; + } + + __vcpu_assign_sys_reg(vcpu, rd->reg, val); + return 0; +} + static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { @@ -3616,7 +3644,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { CTR_EL0_DminLine_MASK | CTR_EL0_L1Ip_MASK | CTR_EL0_IminLine_MASK), - { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility }, + { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility, .set_user = set_svcr }, { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility }, { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, -- 2.47.3