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Mon, 20 Jul 2026 05:15:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66CF.mail.protection.outlook.com (10.167.240.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.245.5 via Frontend Transport; Mon, 20 Jul 2026 05:15:09 +0000 Received: from cix (unknown [172.18.64.61]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 2F58C427CEE0; Mon, 20 Jul 2026 13:15:08 +0800 (CST) From: joakim.zhang@cixtech.com To: mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de Cc: cix-kernel-upstream@cixtech.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joakim Zhang Subject: [PATCH v10 0/4] Add Cix Sky1 AUDSS clock and reset support Date: Mon, 20 Jul 2026 13:15:01 +0800 Message-ID: <20260720051505.1252774-1-joakim.zhang@cixtech.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CF:EE_|KUYPR06MB8916:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 57b78c67-f474-4df0-1e7f-08dee61dde95 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|1800799024|36860700016|82310400026|7416014|376014|56012099006|18002099003|10067099003|3023799007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YR/SpfQx/kzeJnKCK+Vo5Zt0VT+SbuPETw8NO3ZcWwei0SJdzDRs5hwZinqv/mw5ZYLnhVFRosT76FR7OiL/H9NELBECCAAPKoKqfRIeaJTDUUCGkm20AE+2pEEXlhDY8tLKGX2UHIaQnD948h1t+bYAdctRfUvFP6kQ8iYfN7/wMTIohsbbIig/m/ppuiwo7DuPmwO3mNTBYpIA6Yp40AldhFTOY7vn2IbQXMGKwoO58OzV9+m/czcCGZZQct1gYP2znWRAN+wYvPU9a/IrBa0UHwHbrNWVaK1mGioSERMiHKDd4fm93nuQsMRJykxfgpJd0fu49+Dqk0kw6bCXeDPe5cMx7PAjcv1W9OHOvNFuNlspZi1pAFap9qNWWWUJrUgto8WK///KqM/i8zUoT5FbMIjnFWepXPcx39tbBoceb3qJfwH1lm0CvvgcEuj1 X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2026 05:15:09.3347 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 57b78c67-f474-4df0-1e7f-08dee61dde95 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CF.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KUYPR06MB8916 From: Joakim Zhang The Cix Sky1 Audio Subsystem (AUDSS) groups audio-related blocks such as HDA, I2S, DSP, DMA, mailboxes, watchdog and timer behind one Clock and Reset Unit (CRU). The CRU is a single MMIO register block that provides clock muxing, gating and block-level software reset lines for those peripherals. Clock and reset support are submitted in one series because they belong to the same hardware block and share one devicetree node (cix,sky1-audss-cru). The binding, clock indices and reset indices are defined together; the clock driver maps the CRU and instantiates the reset controller as an auxiliary driver on that node. Splitting clk and reset across separate series would leave neither side self-contained: the DTS node needs both providers, and the reset driver has no standalone probe path without the clock driver. --- ChangeLogs: v9->v10: * clk driver: * drop unused linux/of_device.h * enable parent clocks before NOC deassert; assert NOC before disabling clocks on suspend (and reverse on resume) * enable runtime PM only after parent clocks are on; collapse probe error paths into a single fail_pm label * move runtime PM teardown to devm_add_action_or_reset() and drop remove(), so the OF provider is unbound before force_suspend v8->v9: * Reverse Christmas tree order * use devm_clk_hw_register_composite_pdata() * assert reset if clks enabled failed * add pm_ptr v7->v8: * reset Kconfig: drop select REGMAP_MMIO v6->v7: * reset driver: * propagate regmap errors in assert/deassert ops * drop .reset and .status ops (no consumer uses them) * remove regmap fallback path; use parent regmap only * use dev->of_node for rcdev.of_node * drop of_reset_n_cells and dev_set_drvdata() * dt-binding: * Reviewed-by: Krzysztof Kozlowski v5->v6: * rename dt-bindings headers to cix,sky1-audss-cru.h to match compatible * drop status = "okay" from audss_cru node in sky1.dtsi v4->v5: * refactor the driver, using platform_driver for clk and auxiliary_driver for reset. v3->v4: * move both power domain and resets into parset node (audss_cru) * remove "simple-mfd", and change to populate the child node * cix,sky1-audss.h -> cix,sky1-audss-clock.h v2->v3: * clk part: * devm_reset_control_get()->devm_reset_control_get_exclusive() * assert noc reset from suspend * clock parents changes from 6 to 4, and rename the clock names, explain more about this: confirm with our designer, In fact, there are 6 clock sources going into the audio subsystem. audio_clk1 and audio_clk3 are redundant in design and are not actually needed in practice, so they are not shown here. * refine clocks and clock-names property * add detailed description of clocks * drop parent node from clk binding * drop define AUDSS_MAX_CLKS * reset part: * rename reset signal macro, remove _N * drop SKY1_AUDSS_SW_RESET_NUM * switching to compatible-style of defining subnodes in parent schema v1->v2: * remove audss_rst device node since it doesn't has resource, and move to reset-sky1.c driver. * remove hda related which would be sent after this patch set accepted * soc componnet is okay by default from dtsi * fix for audss clk driver: * remove "comment "Clock options for Cixtech audss:"" * add select MFD_SYSCON * move lock and clk_data into struct sky1_audss_clks_priv * const char *name -> const char * const * name * remove CLK_GET_RATE_NOCACHE * divicer -> divider * Reverse Christmas tree order * return reg ? 1 : 0; -> return !!reg; * return ERR_CAST(hw); -> return hw; * of_device_get_match_data(dev) -> device_get_match_data() * add lock from runtime_suspend/resume * loop to more mailing lists Joakim Zhang (4): dt-bindings: soc: cix: add sky1 audss cru controller clk: cix: add sky1 audss clock controller reset: cix: add sky1 audss auxiliary reset driver arm64: dts: cix: sky1: add audss cru .../bindings/soc/cix/cix,sky1-audss-cru.yaml | 92 ++ arch/arm64/boot/dts/cix/sky1.dtsi | 18 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/cix/Kconfig | 16 + drivers/clk/cix/Makefile | 3 + drivers/clk/cix/clk-sky1-audss.c | 1211 +++++++++++++++++ drivers/reset/Kconfig | 13 + drivers/reset/Makefile | 1 + drivers/reset/reset-sky1-audss.c | 137 ++ .../dt-bindings/clock/cix,sky1-audss-cru.h | 60 + .../dt-bindings/reset/cix,sky1-audss-cru.h | 25 + 12 files changed, 1578 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml create mode 100644 drivers/clk/cix/Kconfig create mode 100644 drivers/clk/cix/Makefile create mode 100644 drivers/clk/cix/clk-sky1-audss.c create mode 100644 drivers/reset/reset-sky1-audss.c create mode 100644 include/dt-bindings/clock/cix,sky1-audss-cru.h create mode 100644 include/dt-bindings/reset/cix,sky1-audss-cru.h -- 2.50.1