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Mon, 20 Jul 2026 01:20:18 -0700 (PDT) Received: from hu-uchheda-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38e39e0531asm7233688a91.5.2026.07.20.01.20.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 01:20:17 -0700 (PDT) From: Umang Chheda To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Ruidong Tian , Tony Luck , Borislav Petkov , Umang Chheda Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, faruque.ansari@oss.qualcomm.com, avaneesh.dwivedi@oss.qualcomm.com Subject: [PATCH v2 3/4] arm64: dts: qcom: monaco: add RAS error source nodes Date: Mon, 20 Jul 2026 13:49:53 +0530 Message-Id: <20260720081954.1858180-4-umang.chheda@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260720081954.1858180-1-umang.chheda@oss.qualcomm.com> References: <20260720081954.1858180-1-umang.chheda@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=HeYkiCE8 c=1 sm=1 tr=0 ts=6a5dda43 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=hf7YQE2i2jH5Ah-ZJM4A:9 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: ixJtjh0R2V0G_tJltYFj4aYKDSPldHiW X-Proofpoint-ORIG-GUID: ixJtjh0R2V0G_tJltYFj4aYKDSPldHiW X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIwMDA5MSBTYWx0ZWRfXzZmMWF2yJVHb IUEq4SC7adDiA58xDShUZOufX733Ak/wPRBfXbb2eUZf0k7hzFdCeNcsEZlpEb2diVTIy1SYRpK eyzgmCDdqD7bY35QUNtb64XtMqM4vxk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIwMDA5MSBTYWx0ZWRfXxYxPp7Il1huE olGhc6Xd6c2H8e4GFhd+su0hkZm13sVVqbVJt6eIXxFseeMJQmq2y+qeGzqW6qrLoRnD/hy04iX s84cjGshVoZR50VXZ7ZYWyhW6OE8xOsLVwhj79boRUUXjxdvpRTNVPD9h+mxmPJTByI1JPl3gJH CrcY1boSPiXTxnfdL9X4Rvg/L5vIbqQOTy4CRnyXe8exsZz7Kc2miolCyMBfoJAoATBNAbyBA9R IVWzUDaxetSNxP5gBDlpmL+zafX4O/wpig/yAY2g6jiTogKVPZh6PiaSBHWzyCDFlrQVOU2jJnK qWDNZXB9Uyx/pxHCBFIAxjQmNfeEQDEJeQhlMrlgnJGEQY3ywr03WZDL9vcJd/orfLfPaiPueHa jv/kG4NvEld7qwlZoqiTwnPps3YWmD1MLKs1kajA1fscXQwU/jNbw7RMwbmhgXEpGLAISFv6Y3n 8mtEu0E8SlXTq5nxBoA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_01,2026-07-17_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 suspectscore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607200091 Add RAS error source nodes for the Monaco SoC. Two processor error sources are described: a per-PE node covering the L1/L2 cache hierarchy using a PPI, and two shared L3 cache nodes for the two CPU clusters using SPIs. Co-developed-by: Faruque Ansari Signed-off-by: Faruque Ansari Signed-off-by: Umang Chheda --- arch/arm64/boot/dts/qcom/monaco.dtsi | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 64fc0d592282..4fbd1dc9a147 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -724,6 +724,36 @@ system_pd: power-domain-system { }; }; + ras-l1l2-0 { + compatible = "arm,ras-processor"; + arm,num-records = <1>; + arm,record-impl = /bits/ 64 <0x1>; + arm,status-reporting = /bits/ 64 <0x1>; + cache = <&l2_0>; + interrupts = ; + interrupt-names = "fhi"; + }; + + ras-l3-cluster0 { + compatible = "arm,ras-processor"; + arm,num-records = <2>; + arm,record-impl = /bits/ 64 <0x2>; + arm,status-reporting = /bits/ 64 <0x2>; + cache = <&l3_0>; + interrupts = ; + interrupt-names = "fhi"; + }; + + ras-l3-cluster1 { + compatible = "arm,ras-processor"; + arm,num-records = <2>; + arm,record-impl = /bits/ 64 <0x2>; + arm,status-reporting = /bits/ 64 <0x2>; + cache = <&l3_1>; + interrupts = ; + interrupt-names = "fhi"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; -- 2.34.1