From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CE123CA4B2 for ; Mon, 20 Jul 2026 20:56:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784580974; cv=none; b=RZPGzcfDULfgQPnjb60F2Q/T923relnZjJzucuukapWp9CB/6iaor5T4TSZJHRAwhUDkvQq34Czz1ueel968+dEgSf6w9LgJwEwcC3QebXGt4RQpeTBILoG1tXEo4C0YzCEoWkJschW7p4W93xwBh75ev9O1uEcA7SV5m4XmyHc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784580974; c=relaxed/simple; bh=Fvrh41UOMQtcBoH5Kw2yvPgDFtPZxFVIXgRgzXFB8pM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mK3xbnZnpFhu8nBpKTSsdgYuT4+x41HMVBprrOZffj505PUKv9n6zJ9vKQq8r8qHB801CJUJ+tPU49XQYKjpKc0dTszeaj2NLZ4Dw90jzkfHfCjE2XbkP1skCGLUSzAYznefQG1iL28BEJeBuZzmzK2zL/ZGiMIAt427t/WEoUY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=EakguxlX; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="EakguxlX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1784580971; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SkFbcmN22+jwJHxujtPfv4GRpg6PFI3N28PCo7GA/48=; b=EakguxlXxQyQa9R7kB28NYlB+AN3CvxUNsH3I4XkbqhxtoUTSAqXU/PThnBp+O/yyZlQ1Y MkrYPlaIIWzQsI3yLIM/S50vqQk9OduV+Fl9uIOHRWhcOAM5jYx+Z1v3lo4OTxkpDORgU4 JeD3nHFYxFSq4IIaQ5QWVLir43txWag= Received: from mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-519--4j-v273McKzSOej8fnPQw-1; Mon, 20 Jul 2026 16:56:07 -0400 X-MC-Unique: -4j-v273McKzSOej8fnPQw-1 X-Mimecast-MFC-AGG-ID: -4j-v273McKzSOej8fnPQw_1784580965 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 0A4BC195DE34; Mon, 20 Jul 2026 20:56:05 +0000 (UTC) Received: from GoldenWind.redhat.com (unknown [10.22.88.114]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 9E5AE1955F78; Mon, 20 Jul 2026 20:56:02 +0000 (UTC) From: Lyude Paul To: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: "Faith Ekstrand" , "Dave Airlie" , "Leandro Ribeiro" , "Maarten Lankhorst" , "Luca Ceresoli" , "Kees Cook" , "Marco Crivellari" , "Simona Vetter" , "Pekka Paalanen" , "David Airlie" , "Thomas Zimmermann" , "Maxime Ripard" , "Danilo Krummrich" , "Daniel Stone" , "James Jones" , "Lyude Paul" Subject: [PATCH v2 2/3] drm/nouveau/kms/nv50-: Introduce nv50_wndw_default_state() Date: Mon, 20 Jul 2026 16:43:56 -0400 Message-ID: <20260720205541.257781-3-lyude@redhat.com> In-Reply-To: <20260720205541.257781-1-lyude@redhat.com> References: <20260720205541.257781-1-lyude@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 While we don't currently read-in the hardware state of planes, now that we're about to start exposing blend properties for all planes that can support alpha channels: We need to make sure that the initial atomic state for a wndw always starts off with a supported value in pixel_blend_mode. The easiest way to do this is to introduce a nv50_wndw_default_state() function, and use it in nv50_display_read_hw_state() - and use that function to enforce a valid value for pixel_blend_mode during driver startup. Signed-off-by: Lyude Paul Fixes: 860e748bddcc ("drm: ensure blend mode supported if pixel format with alpha exposed") --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 4 ++++ drivers/gpu/drm/nouveau/dispnv50/wndw.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/nouveau/dispnv50/wndw.h | 1 + 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 364227f5456f1..2c66e480b5116 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -2768,6 +2768,7 @@ nv50_display_read_hw_state(struct nouveau_drm *drm) { struct drm_device *dev = drm->dev; struct drm_encoder *encoder; + struct drm_plane *plane; struct drm_modeset_acquire_ctx ctx; struct nv50_disp *disp = nv50_disp(dev); int ret; @@ -2781,6 +2782,9 @@ nv50_display_read_hw_state(struct nouveau_drm *drm) nv50_display_read_hw_or_state(dev, disp, nouveau_encoder(encoder)); } + drm_for_each_plane(plane, dev) + nv50_wndw_default_state(nv50_wndw(plane)); + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 2635458d52acc..0f331f47bded8 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -848,6 +848,28 @@ static const u64 nv50_cursor_format_modifiers[] = { DRM_FORMAT_MOD_INVALID, }; +/* + * Setup defaults for the atomic wndw state + */ +void +nv50_wndw_default_state(struct nv50_wndw *wndw) +{ + struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state); + const unsigned int blend_modes = wndw->func->blend_modes; + + drm_modeset_lock_assert_held(&wndw->plane.mutex); + + /* Ensure the plane's atomic state didn't default to a pixel_blend_mode we don't support */ + if (blend_modes && (!(armw->state.pixel_blend_mode & blend_modes))) { + if (blend_modes & BIT(DRM_MODE_BLEND_COVERAGE)) + armw->state.pixel_blend_mode = DRM_MODE_BLEND_COVERAGE; + else if (blend_modes & BIT(DRM_MODE_BLEND_PREMULTI)) + armw->state.pixel_blend_mode = DRM_MODE_BLEND_PREMULTI; + else if (blend_modes & BIT(DRM_MODE_BLEND_PIXEL_NONE)) + armw->state.pixel_blend_mode = DRM_MODE_BLEND_PIXEL_NONE; + } +} + int nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, enum drm_plane_type type, const char *name, int index, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 81af5c3369d4c..13f06b7b67611 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -46,6 +46,7 @@ void nv50_wndw_flush_clr(struct nv50_wndw *, u32 *interlock, bool flush, struct nv50_wndw_atom *); void nv50_wndw_ntfy_enable(struct nv50_wndw *, struct nv50_wndw_atom *); int nv50_wndw_wait_armed(struct nv50_wndw *, struct nv50_wndw_atom *); +void nv50_wndw_default_state(struct nv50_wndw *wndw); struct nv50_wndw_func { int (*acquire)(struct nv50_wndw *, struct nv50_wndw_atom *asyw, -- 2.55.0