From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49F1532470E for ; Mon, 20 Jul 2026 21:52:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784584338; cv=none; b=qB3kaVj2Nw7R4IOy2VXODHQu/1P2Xz6pTZWj3uDdQ/2yiVIvyKY+pWMhQVdyEMs3H/FFmzoS7zCIpm1xtwlEfnDzifdcNu0cIYWAdzsgX4XvcALIKW8DO2nFJBV3uELAK2sq6BPith5d/YvRT6wFhJ+lTS5yNWb7jPbpNzO2nwY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784584338; c=relaxed/simple; bh=SSI1DP7S2/kamg20sFeY6V/xMvh9s5924rOIetvqTyo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lc1/pC6fnQ02Baxfc8+3d8dH9cpcxC9vMOLZlv5suOCw/rCowwttVej4fqf1tDJzC/35cjdtFIEBEVm9MClVHpBTkOQIB/sV9dq3i0e+/l53T7QoOhKSU8iPcGFglGMqxc2HxJB+uQpl2upf4FBytyDkBqEMZcOxe/yr/KuIxGk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=iNMeOSg6; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="iNMeOSg6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1784584336; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4Abm8mO2p2VoBX8nFEzar8JO9CYwOTrVGq6n2nwojj8=; b=iNMeOSg6wvK3hMtEfPk4teUzIf8WvRHHQor1Lt7vzqe8fWrfb7h0Zop/MpLaIg/zcaW/bA egT4JFz515yI9Bix3a0HRv/CXcYYcmO3JXvDRrm631nNHeT9DuUcg9Kp+NWKCQ361A4+qy s3fhMr6OgLnr8tAOQp3PX38mQiAWeF8= Received: from mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-82-WZdwZoT7NWSdinl9n9f_vA-1; Mon, 20 Jul 2026 17:52:10 -0400 X-MC-Unique: WZdwZoT7NWSdinl9n9f_vA-1 X-Mimecast-MFC-AGG-ID: WZdwZoT7NWSdinl9n9f_vA_1784584328 Received: from mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 4546C1964CD2; Mon, 20 Jul 2026 21:52:08 +0000 (UTC) Received: from GoldenWind.redhat.com (unknown [10.22.88.114]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id DA1F1180075F; Mon, 20 Jul 2026 21:52:05 +0000 (UTC) From: Lyude Paul To: nouveau@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: "Faith Ekstrand" , "Dave Airlie" , "Leandro Ribeiro" , "Maarten Lankhorst" , "Marco Crivellari" , "Kees Cook" , "Simona Vetter" , "Pekka Paalanen" , "David Airlie" , "Thomas Zimmermann" , "Maxime Ripard" , "Danilo Krummrich" , "Jani Nikula" , "Daniel Stone" , "James Jones" , "Lyude Paul" Subject: [PATCH v3 2/3] drm/nouveau/kms/nv50-: Introduce nv50_wndw_default_state() Date: Mon, 20 Jul 2026 17:36:17 -0400 Message-ID: <20260720215058.398210-3-lyude@redhat.com> In-Reply-To: <20260720215058.398210-1-lyude@redhat.com> References: <20260720215058.398210-1-lyude@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 While we don't currently read-in the hardware state of planes, now that we're about to start exposing blend properties for all planes that can support alpha channels: We need to make sure that the initial atomic state for a wndw always starts off with a supported value in pixel_blend_mode. The easiest way to do this is to introduce a nv50_wndw_default_state() function, and use it in nv50_display_read_hw_state() - and use that function to enforce a valid value for pixel_blend_mode during driver startup. Signed-off-by: Lyude Paul Fixes: 860e748bddcc ("drm: ensure blend mode supported if pixel format with alpha exposed") --- V3: * Fix incorrect bitmask checking in nv50_wndw_default_state() drivers/gpu/drm/nouveau/dispnv50/disp.c | 4 ++++ drivers/gpu/drm/nouveau/dispnv50/wndw.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/nouveau/dispnv50/wndw.h | 1 + 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 364227f5456f1..2c66e480b5116 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -2768,6 +2768,7 @@ nv50_display_read_hw_state(struct nouveau_drm *drm) { struct drm_device *dev = drm->dev; struct drm_encoder *encoder; + struct drm_plane *plane; struct drm_modeset_acquire_ctx ctx; struct nv50_disp *disp = nv50_disp(dev); int ret; @@ -2781,6 +2782,9 @@ nv50_display_read_hw_state(struct nouveau_drm *drm) nv50_display_read_hw_or_state(dev, disp, nouveau_encoder(encoder)); } + drm_for_each_plane(plane, dev) + nv50_wndw_default_state(nv50_wndw(plane)); + DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 2635458d52acc..dfa1ba45acd99 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -848,6 +848,28 @@ static const u64 nv50_cursor_format_modifiers[] = { DRM_FORMAT_MOD_INVALID, }; +/* + * Setup defaults for the atomic wndw state + */ +void +nv50_wndw_default_state(struct nv50_wndw *wndw) +{ + struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state); + const unsigned int blend_modes = wndw->func->blend_modes; + + drm_modeset_lock_assert_held(&wndw->plane.mutex); + + /* Ensure the plane's atomic state didn't default to a pixel_blend_mode we don't support */ + if (blend_modes && (!(BIT(armw->state.pixel_blend_mode) & blend_modes))) { + if (blend_modes & BIT(DRM_MODE_BLEND_COVERAGE)) + armw->state.pixel_blend_mode = DRM_MODE_BLEND_COVERAGE; + else if (blend_modes & BIT(DRM_MODE_BLEND_PREMULTI)) + armw->state.pixel_blend_mode = DRM_MODE_BLEND_PREMULTI; + else if (blend_modes & BIT(DRM_MODE_BLEND_PIXEL_NONE)) + armw->state.pixel_blend_mode = DRM_MODE_BLEND_PIXEL_NONE; + } +} + int nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, enum drm_plane_type type, const char *name, int index, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 81af5c3369d4c..13f06b7b67611 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -46,6 +46,7 @@ void nv50_wndw_flush_clr(struct nv50_wndw *, u32 *interlock, bool flush, struct nv50_wndw_atom *); void nv50_wndw_ntfy_enable(struct nv50_wndw *, struct nv50_wndw_atom *); int nv50_wndw_wait_armed(struct nv50_wndw *, struct nv50_wndw_atom *); +void nv50_wndw_default_state(struct nv50_wndw *wndw); struct nv50_wndw_func { int (*acquire)(struct nv50_wndw *, struct nv50_wndw_atom *asyw, -- 2.55.0