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Tue, 21 Jul 2026 00:07:30 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84c2adcc74csm7080833b3a.18.2026.07.21.00.07.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2026 00:07:30 -0700 (PDT) From: Taniya Das Subject: [PATCH v2 0/6] clk: qcom: Add Nord multimedia clock controller support Date: Tue, 21 Jul 2026 12:37:15 +0530 Message-Id: <20260721-nords_mm_v1-v2-0-17e5a445a512@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAKMaX2oC/1WM0QrCIBiFX2X81zmcM3O76j1ijKWuCanlX1IM3 z0bdBEcDnwHzrcCmmgNQl+tEE2yaIMvwHYVqGXyF0OsLgyMMkEFo8SHqHF0bkwN6c4HrfncMS0 0lMctmtm+NttpKLxYfIT43uSp+a4/T/vnKaFECqok37edpPwYEOv7c7qq4FxdCoac8wdvK3wZr QAAAA== X-Change-ID: 20260620-nords_mm_v1-9b7dd4f92d6d To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Shawn Guo , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das , Konrad Dybcio X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-GUID: 9tAplMDz4TKn12S__DlEvf0sTrRpMVfk X-Proofpoint-ORIG-GUID: 9tAplMDz4TKn12S__DlEvf0sTrRpMVfk X-Authority-Analysis: v=2.4 cv=e+U2j6p/ c=1 sm=1 tr=0 ts=6a5f1ab3 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=vI_4KLquzuGg7hnt8WQA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA3MyBTYWx0ZWRfX+eJJQVY4wII3 UCZvsb96C6iraw0zozhybqtsD1uyDaV4jMQKLR92jRnqyBuyARV/X6W+ES6drjdXkKXgFSCYzlk 191ImtlY96EXLtf4Z46lZO4aPZgXJsA= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA3MyBTYWx0ZWRfX1svC6cBqsoui sv7oiZ39aMX1uK6pSUJsAHx+35OGiodHIteqDVrrws/ukOodQh9Im9r5wCeKKtIrti+6F97v2s7 EBekmN+o/MJzY/26cxonUrXIkumev0DvhpUVpvp1AZwoGHmdXQLof7G5e9sVd8a9qh823ffcadg V1mzvTxSSfw/zlZCLzhMGuXSvISGj0y9MXwkhq1lo3b/vfZ5/ym3GgIQH/3TVrOiZ/w91d0fY/d YD2yYA0RWcWic2pPKUiNxqMUaASTrubWbLqueHwcm/kWDTfUjIkMxmcwfK8Q5VNVL2VZYLTn1ov E2GYrgsJyWHgOb5D5joZsZK2rjGs347sOAGMDQ1g/l9yovG29Zfc31KH6SgJWbZfSIDEP2HyZ4W iS4pSl/PPKl9J+dZZwbc773Bs/m85p/fgfD1xAfYrPd2B0I7PRII/pOjms0F7TihuJIEI2a5FYW m9iuj2MkIaavXW5x4lw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210073 This series adds clock controller support for the multimedia subsystems on the Qualcomm Nord SoC platform, along with two fixes for always-on clocks that were incorrectly exposed as controllable branches. The Nord platform is a multi-cluster SoC that includes dedicated clock controllers for the display and graphics subsystems. This series adds: - DT bindings and driver support for the two display clock controller instances (DISPCC_0 and DISPCC_1). - DT bindings and driver support for the two GPU clock controller instances (GPUCC and GPU2CC). - A fix for the GCC-Nord driver to mark PCIe link AHB and XO clocks as critical CBCRs instead of gatable clk_branch instances. - A fix for the NEGCC-Nord driver to mark the GPU2 CFG clock as a critical CBCR instead of a controllable clk_branch. The two fix patches carry Fixes: tags pointing to the original Nord GCC commit and are candidates for stable backport. Changes in v2: - Split the GPU2CC-specific clock and reset IDs (MND1X_1_GFX3D_CLK, FF_BCR, GMU_BCR) out of the shared qcom,nord-gpucc.h dt-bindings header into a new qcom,nord-gpu2cc.h header, since GPUCC and GPU2CC are separate DT nodes with independent ID namespaces. - Updated qcom,nord-dispcc.h comments to reflect that the header now covers both the DISPCC_0 and DISPCC_1 instances. - Dropped unnecessary and includes from dispcc0-nord.c, dispcc1-nord.c, gpucc-nord.c, and gpu2cc-nord.c. - Link to v1: https://lore.kernel.org/r/20260623-nords_mm_v1-v1-0-860c84539804@oss.qualcomm.com Signed-off-by: Taniya Das --- Taniya Das (6): clk: qcom: gcc-nord: mark PCIe link clocks as critical clk: qcom: negcc-nord: keep GPU2 CFG clock enabled via critical CBCR dt-bindings: clock: qcom: Document Nord display clock controller clk: qcom: Add Nord display clock controller support dt-bindings: clock: qcom: Document Nord GPU clock controllers clk: qcom: gpucc: Add Nord graphics clock controller support .../bindings/clock/qcom,sm8450-gpucc.yaml | 3 + .../bindings/clock/qcom,sm8550-dispcc.yaml | 3 + drivers/clk/qcom/Kconfig | 22 + drivers/clk/qcom/Makefile | 2 + drivers/clk/qcom/dispcc0-nord.c | 2004 ++++++++++++++++++++ drivers/clk/qcom/dispcc1-nord.c | 2004 ++++++++++++++++++++ drivers/clk/qcom/gcc-nord.c | 37 +- drivers/clk/qcom/gpu2cc-nord.c | 545 ++++++ drivers/clk/qcom/gpucc-nord.c | 593 ++++++ drivers/clk/qcom/negcc-nord.c | 22 +- include/dt-bindings/clock/qcom,nord-dispcc.h | 115 ++ include/dt-bindings/clock/qcom,nord-gpu2cc.h | 47 + include/dt-bindings/clock/qcom,nord-gpucc.h | 48 + 13 files changed, 5399 insertions(+), 46 deletions(-) --- base-commit: 3ce97bd3c4f18608335e709c24d6a40e7036cab8 change-id: 20260620-nords_mm_v1-9b7dd4f92d6d Best regards, -- Taniya Das