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Tue, 21 Jul 2026 00:08:01 -0700 (PDT) X-Received: by 2002:a05:6a00:f8d:b0:848:60a2:4e9b with SMTP id d2e1a72fcca58-84c294d4b0bmr17751554b3a.42.1784617681159; Tue, 21 Jul 2026 00:08:01 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84c2adcc74csm7080833b3a.18.2026.07.21.00.07.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2026 00:08:00 -0700 (PDT) From: Taniya Das Date: Tue, 21 Jul 2026 12:37:20 +0530 Subject: [PATCH v2 5/6] dt-bindings: clock: qcom: Document Nord GPU clock controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260721-nords_mm_v1-v2-5-17e5a445a512@oss.qualcomm.com> References: <20260721-nords_mm_v1-v2-0-17e5a445a512@oss.qualcomm.com> In-Reply-To: <20260721-nords_mm_v1-v2-0-17e5a445a512@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Shawn Guo , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-ORIG-GUID: NuSHwZB4UDuvNIyb0ABUn-aIT0Jc7iQB X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA3MyBTYWx0ZWRfX9JLw7TAIXPWW fpgI3moy2jNCZSkV5WSPFOiMwTo4Pm8eFs/pxTK9d5N+8gyvmmbU1ewJbFQE1iUKfx+iBMD11Q6 KDmmN8DFc3C2bnRUUMcxRdEKUnqxpWA= X-Proofpoint-GUID: NuSHwZB4UDuvNIyb0ABUn-aIT0Jc7iQB X-Authority-Analysis: v=2.4 cv=Sb7HsPRu c=1 sm=1 tr=0 ts=6a5f1ad2 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=bOuFlZkiYT1K-aWiZo8A:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA3MyBTYWx0ZWRfX+m1EhgTW0JwH 0NCfv/Qrm78VqIgzOIjgwjd7lujVU6uuZnegpbLQxtX6g5WVS19sexGXtUXmd4FwCnphHdBlvoh HqCFRa7xGy7Ji1hgOrGudEyiECvBopafNVoUZ8J0M2wV6O0Wu8uUqutKWedkswfjSya/teX1JC0 GaVB2aH18omP+aJE0eIG3R3swh2tHKSFP9hZ0mxIEQFb7iYy1f2lrPEQRke487gomYSKYOF8GCE UNC5MMpTptC0CSaYg5du2zyZOahIWt/QaeZfkE2Zw4Fxo97oLm7UFxy0vbacYQG1qxraR5b7eEA +TXa0qQiiDqtFuWHJ06Cm7sUWjmZjax/NUeNo4D4y+MO6yx8anENCkaPqUrNiAu80rNlUbr8xF/ cs/oxT0hbC3ldyysbiuQI1M8lCYjc9EQm07qA/SyBo7fhM+1mpMZiX7X4nCo1/X7vw2MB9mXPQE npbEPlo38RaDGdyBvBw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 spamscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210073 Add Device Tree binding documentation for the GPU clock controllers on the Qualcomm Nord platform. The platform includes two GPU clock controller instances, GPUCC and GPUCC2. Document the compatible strings for both controllers. Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sm8450-gpucc.yaml | 3 ++ include/dt-bindings/clock/qcom,nord-gpu2cc.h | 47 +++++++++++++++++++++ include/dt-bindings/clock/qcom,nord-gpucc.h | 48 ++++++++++++++++++++++ 3 files changed, 98 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index fdbdf605ee695637512ce4f98c9b6fcfacb9154f..ba85692240e07a4ed8e69c6b61847c5601b32fa0 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -18,6 +18,7 @@ description: | include/dt-bindings/clock/qcom,glymur-gpucc.h include/dt-bindings/clock/qcom,kaanapali-gpucc.h include/dt-bindings/clock/qcom,milos-gpucc.h + include/dt-bindings/clock/qcom,nord-gpucc.h include/dt-bindings/clock/qcom,sar2130p-gpucc.h include/dt-bindings/clock/qcom,sm4450-gpucc.h include/dt-bindings/clock/qcom,sm8450-gpucc.h @@ -33,6 +34,8 @@ properties: - qcom,glymur-gpucc - qcom,kaanapali-gpucc - qcom,milos-gpucc + - qcom,nord-gpu2cc + - qcom,nord-gpucc - qcom,sar2130p-gpucc - qcom,sm4450-gpucc - qcom,sm8450-gpucc diff --git a/include/dt-bindings/clock/qcom,nord-gpu2cc.h b/include/dt-bindings/clock/qcom,nord-gpu2cc.h new file mode 100644 index 0000000000000000000000000000000000000000..3886af669c61003f71e2da28f939f273e761c653 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-gpu2cc.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_2_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_GPU_2_CC_NORD_H + +/* GPU_2_CC clocks */ +#define GPU_2_CC_AHB_CLK 0 +#define GPU_2_CC_CRC_AHB_CLK 1 +#define GPU_2_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_2_CC_CX_FF_CLK 3 +#define GPU_2_CC_CX_GMU_CLK 4 +#define GPU_2_CC_CXO_AON_CLK 5 +#define GPU_2_CC_CXO_CLK 6 +#define GPU_2_CC_DEMET_CLK 7 +#define GPU_2_CC_FF_CLK_SRC 8 +#define GPU_2_CC_FREQ_MEASURE_CLK 9 +#define GPU_2_CC_GMU_CLK_SRC 10 +#define GPU_2_CC_GPU_SMMU_VOTE_CLK 11 +#define GPU_2_CC_HUB_AON_CLK 12 +#define GPU_2_CC_HUB_CLK_SRC 13 +#define GPU_2_CC_HUB_CX_INT_CLK 14 +#define GPU_2_CC_MEMNOC_GFX_CLK 15 +#define GPU_2_CC_MND1X_0_GFX3D_CLK 16 +#define GPU_2_CC_MND1X_1_GFX3D_CLK 17 +#define GPU_2_CC_PLL0 18 +#define GPU_2_CC_PLL1 19 +#define GPU_2_CC_SLEEP_CLK 20 + +/* GPU_2_CC power domains */ +#define GPU_2_CC_CX_GDSC 0 +#define GPU_2_CC_GX_GDSC 1 + +/* GPU_2_CC resets */ +#define GPU_2_CC_ACD_BCR 0 +#define GPU_2_CC_CB_BCR 1 +#define GPU_2_CC_CX_BCR 2 +#define GPU_2_CC_FAST_HUB_BCR 3 +#define GPU_2_CC_FF_BCR 4 +#define GPU_2_CC_GFX3D_AON_BCR 5 +#define GPU_2_CC_GMU_BCR 6 +#define GPU_2_CC_GX_BCR 7 +#define GPU_2_CC_XO_BCR 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,nord-gpucc.h b/include/dt-bindings/clock/qcom,nord-gpucc.h new file mode 100644 index 0000000000000000000000000000000000000000..3cc348be5668b309a151665fc29bdcb30c480740 --- /dev/null +++ b/include/dt-bindings/clock/qcom,nord-gpucc.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_NORD_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_NORD_H + +/* GPU_CC clocks */ +#define GPU_CC_ACD_GFX3D_CLK 0 +#define GPU_CC_ACMU_CLK 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CRC_AHB_CLK 3 +#define GPU_CC_CX_ACCU_SHIFT_CLK 4 +#define GPU_CC_CX_FF_CLK 5 +#define GPU_CC_CX_GMU_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_DEMET_CLK 9 +#define GPU_CC_DPM_CLK 10 +#define GPU_CC_FF_CLK_SRC 11 +#define GPU_CC_FREQ_MEASURE_CLK 12 +#define GPU_CC_GMU_CLK_SRC 13 +#define GPU_CC_GPU_SMMU_VOTE_CLK 14 +#define GPU_CC_HUB_AON_CLK 15 +#define GPU_CC_HUB_CLK_SRC 16 +#define GPU_CC_HUB_CX_INT_CLK 17 +#define GPU_CC_HUB_DIV_CLK_SRC 18 +#define GPU_CC_MEMNOC_GFX_CLK 19 +#define GPU_CC_MND1X_GFX3D_CLK 20 +#define GPU_CC_PLL0 21 +#define GPU_CC_PLL1 22 +#define GPU_CC_SLEEP_CLK 23 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +/* GPU_CC resets */ +#define GPU_CC_ACD_BCR 0 +#define GPU_CC_CB_BCR 1 +#define GPU_CC_CX_BCR 2 +#define GPU_CC_FAST_HUB_BCR 3 +#define GPU_CC_GFX3D_AON_BCR 4 +#define GPU_CC_GX_BCR 5 +#define GPU_CC_XO_BCR 6 + +#endif -- 2.34.1