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From: Sudeep Holla <sudeep.holla@kernel.org>
To: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
Cc: Daniel Lezcano <daniel.lezcano@oss.qualcomm.com>,
	Sudeep Holla <sudeep.holla@kernel.org>,
	Thomas Gleixner <tglx@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	Pavel Machek <pavel@kernel.org>, Len Brown <lenb@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Lorenzo Pieralisi <lpieralisi@kernel.org>,
	Will Deacon <will@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2] arm64: Disallow disabling boot CPU based on config
Date: Tue, 21 Jul 2026 15:05:16 +0100	[thread overview]
Message-ID: <20260721-towering-orchid-foxhound-d804bc@sudeepholla> (raw)
In-Reply-To: <05081037-9ed8-4e0d-8480-cfa45e950727@oss.qualcomm.com>

On Tue, Jul 21, 2026 at 02:58:49PM +0530, Sneh Mankad wrote:
> 
> 
> On 06-Jul-26 2:46 PM, Sudeep Holla wrote:
> > On Sat, Jul 04, 2026 at 08:43:39AM +0200, Daniel Lezcano wrote:
> >>
> >> Hi Sudeep,
> >>
> >> Le 03/07/2026 à 17:51, Sudeep Holla a écrit :
> >>> (It is always good to cc all PSCI maintainer for any ARM64 CPU
> >>> hotpug/suspend related changes)
> >>>
> >>> On Fri, Jul 03, 2026 at 04:50:02PM +0530, Sneh Mankad wrote:
> >>>> The Qualcomm SoCs like LeMans, Monaco support suspend to ram which leads
> >>>> the SoC to ACPI S3 similar state where SoC is turned off and DDR is
> >>>> retained. The hardware design on these SoCs forces a constraint to suspend
> >>>> and resume the system on boot CPU / CPU0.
> >>>>
> >>> And you fail to explain why they have that constraint.
> >>>
> > 
> > I still need the above to understand the issue/constraint better.
> 
> Above mentioned SoCs have boot CPU fixed to CPU0 in HW, whenever SoC boots
> up/cold boots it starts with CPU0.
> 
> These SoCs support suspend to ram which leads to ACPI S3 similar state
> (where SoC is turned off and DDR is retained).
> PSCI SYSTEM_SUSPEND typically will be executed on boot core itself unless it
> is already offlined and non boot CPUs gets offlined using PSCI CPU_OFF.
> 
> As HW constraint always makes the SoC to boot with boot CPU, consider a
> scenario, where
> 
> Boot CPU is already disabled / offline => suspend to ram is triggered => SoC
> enters ACPI S3 similar state (only DDR is retained and rest of the SoC is
> off).
> <So far good>

Not really, see below ...

> 
> External wake up arrives (say power key press) => SoC starts booting with
> CPU0 => CPU0 becomes first one to "land" in kernel now.
> 

Ideally the firmware could have handled it by booting/waking the suspended
CPU and turning itself off even if it is some h/w limitation to ensure
the firmware is PSCI spec compliant.

> Kernel may later bring up other non-boot CPUs via PSCI CPU_ON calls.
> However Kernel had already marked CPU0 as disabled/ offline but same ended
> up in kernel without PSCI CPU_ON call.
> 

... You resumed back on a wrong CPU.


> To prevent this inconsistent state, before starting suspend to ram, need to
> make sure CPU0 is always online from kernel/ disable offlining of the boot CPU.
> 

At least not in the way this patch does. Kconfig is not an option. Why is
the firmware not handling it properly ? Just resuming random CPU into the
kernel is firmware bug which either needs to be handled as f/w errata
or good if the firmware can be fixed.

> Although the HW constraint needs boot CPU to be online only when suspend to
> ram is triggered, current patch disallows disabling it for simplicity.
> 

That's very strange, so it sounds like not a real h/w constrain to make CPU0
as non-hotpluggable. PSCI CPU_SUSPEND resume path must handle wake up on
wrong CPU correctly and land/resume on the correct CPU in the kernel.

> > 
> >>> Is it because some secure context is not allowed to migrate ?
> >>>
> >>> We already have a mechanism for that in place and this hack is not at all
> >>> required.
> >> Do you mean a mechanism for the secure context or for preventing CPU0 ?
> >>
> > 
> > I meant constraint based on secure context.
> > 
> 
> This is not because secure context not allowed to migrate but above
> mentioned HW constraints.
> 

Sure not secure context related but a HW constraint that secure/PSCI
firmware ignored to handle correctly.

Fix the firmware or explore ways to handle it as FW errata.

-- 
Regards,
Sudeep

      parent reply	other threads:[~2026-07-21 14:05 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-03 11:20 Sneh Mankad
2026-07-03 14:28 ` Mark Rutland
2026-07-03 21:09   ` Thomas Gleixner
2026-07-21  6:59   ` Sneh Mankad
2026-07-21 13:04     ` Mark Rutland
2026-07-21 13:53       ` Sudeep Holla
2026-07-28 10:31         ` Ulf Hansson
2026-07-03 15:51 ` Sudeep Holla
2026-07-04  6:43   ` Daniel Lezcano
2026-07-06  9:16     ` Sudeep Holla
2026-07-09 13:00       ` Daniel Lezcano
2026-07-21  9:28       ` Sneh Mankad
2026-07-21 13:00         ` Mark Rutland
2026-07-21 14:05         ` Sudeep Holla [this message]

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