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[76.11.42.59]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-5c2c648944esm390996e0c.10.2026.07.21.12.38.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2026 12:38:05 -0700 (PDT) From: Ryan Wilbur To: ilpo.jarvinen@linux.intel.com Cc: andriy.shevchenko@linux.intel.com, gregkh@linuxfoundation.org, hvilleneuve@dimonoff.com, jirislaby@kernel.org, john.ogness@linutronix.de, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, m.felsch@pengutronix.de, rwilbur633@gmail.com, stable@vger.kernel.org Subject: Re: [PATCH v2] serial: 8250: clear a stuck RX-timeout interrupt with an empty FIFO Date: Tue, 21 Jul 2026 16:37:51 -0300 Message-Id: <20260721193751.22760-1-rwilbur633@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit > I suspect Andy meant you should put this into hw specific file into a > hw-specific handle_irq. That could be setup in 8250_of.c, it already > seems to do something like that for some specific type. Thanks. I'll move the fix out of 8250_port.c into a PORT_LPC3220 handle_irq, wired up in 8250_of.c the same way fsl8250_handle_irq is, with the handler logic following dw8250_handle_irq's empty-FIFO RX-timeout read. > (8250_dw include check for LSR_BI bit and this one doesn't seem > include that bit, not sure if that's an oversight or intentional > difference [...]) The missing LSR_BI check was an oversight, I'll gate on !(LSR & (UART_LSR_DR | UART_LSR_BI)) to match dw. > So 3rd alternative would be to add e.g. UART_BUG_SPURIOUSRXTO but again > there are the per driver variations. [...] definitely cleaner approach > than copy-pasting this code around. I'll go with the per device handler over the UART_BUG_SPURIOUSRXTO callback because I can only test LPC32xx and I'm not comfortable touching drivers I can't explicitly test against.