From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31B613A963C for ; Wed, 22 Jul 2026 06:36:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784702195; cv=none; b=CAlJBCNkag99OIhpeuRb2E+XeR6bmh1oHOEx0iRXNK/2NNWrDKSdFsED2shrq4FkMUpsxVC8RBrv7/Ssu5D7Ee+H5GJMUFDnR1EDrHfqA/4yQktqqDEUuiTVNpJaW/TVr1ZR6nnL+j1rWdHp9ePnJndn345QI+bE9xf/b+ltoJY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784702195; c=relaxed/simple; bh=xwiwed+YWzAlxad0yWcCPqbevU3q9KR+updrF6TdV7A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mR+8GoLZgo6IJKC+/wdmRgplwFiYT+EqSizv+Hfm/ZWv5909nymySPCbnMS/tsOvBOqNp7HjRVh9Yhd8Mt+10JcPI7VUXkuelWq9FMsKVprA7MejjGcgZPXJMmN1X9T6n6ufivSfi1x7CZBAolsW64hypWCctj+sM+QlXiZwYoQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=P0dK7G7r; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=GYwPDVBP; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="P0dK7G7r"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="GYwPDVBP" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66M54CRH3474518 for ; Wed, 22 Jul 2026 06:36:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= VeNdAJLI50rwT6a6MA64hU5opQaYoTEBW1fpBic2B3U=; b=P0dK7G7rYPmB6TLy NDh9Xy0gn0SzcTa+Iqq+oMawFR0/rw7XccM29K39fo2zp0neGNI+DQPV6wlWZCEc 1LUttBlICu0q5U87xKgjAhtLwRIIAw5BnySh26/3WHC5bdX1TWAy7+sTq6NypfNj bx3we3V5szCRyFjLQd92nNYJlZ/2S0u0cXtAwrq/sErJgz7oASyCDX1eQ9PCKKoN 43KuE+/a//gWhVes/DZP6w76rce4kf1b6vGoQSmyYFaHFnX1LS//yWRyaTHEQX4+ /uVNM7aVD3mylVoCIwC1eb/PI85ztJ7kWORKgghmyUXduFAuUt07cI+xyXOjA1no UshReg== Received: from mail-qt1-f199.google.com (mail-qt1-f199.google.com [209.85.160.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fjd6ftm6h-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 22 Jul 2026 06:36:32 +0000 (GMT) Received: by mail-qt1-f199.google.com with SMTP id d75a77b69052e-51c0199faafso187488321cf.3 for ; Tue, 21 Jul 2026 23:36:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784702191; x=1785306991; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=VeNdAJLI50rwT6a6MA64hU5opQaYoTEBW1fpBic2B3U=; b=GYwPDVBP+JiKGvqzj0z1iJ+1qZebBC9NNKAh5L6FrM5ZQYc4RxUhoEPKIZcCa3Hawk 6DqGdotNMKoCxgA8EkzBdv4ReJtsNIXk6wICh8G2PAu34qUtTzRCvaUJ47fK1XEGrRlG yY7QGdr6pt1uh1WkeX9DAoG6QJKT1KgVQYXAwMwLnfSkv5bJW9RpkpprJ5lzdbr7+rNX NEZ8qW/0m3WzygfB16/wTWFL6+7nm2X2c4Utu6WB2BwB+dvzf/UJty4vhyguYc5Qgvqm HU/QrRsFldt8LqSTeWsbcxq7gBOIcNLjlP0KlM60EJvU6UgKs3HmgzhtQ9helDQJQZ/i kMzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784702191; x=1785306991; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=VeNdAJLI50rwT6a6MA64hU5opQaYoTEBW1fpBic2B3U=; b=DwB/vi4x1XINQXD9sQfE7b1kOa+ukpEV77kSlb8ML5kd0VByjDoo0OLIPUwX4ivlYb Vv4CTftsRYan9WaP5QuLnx3xcgVj9SGVnPYMWq1qXYaqLW/aaK36vcY7XoSjwAxxGlSi lGw+U5j5ph2abj1GAyeFYMf6FW9yYw/+aA9k/JLO6hxy/TEg2FhNzr1bKwTDX6uCoYoR Fq/f3LapYJMkf376IxJHpFdGxC6kDKrSt99DDHUb5EpANPF4FedErkmRfPyEfjd6jlmt lrUKklfCFDcu1pYAAIthTXI6GyG+5v6JdVYdyP0rUZQh+0KV66CDW9iBazDL9Q2zlfvD JI+A== X-Forwarded-Encrypted: i=1; AHgh+RryqfaWtQ1asCI6wNmeXsyGkrf1lSLEqe7Pu/8QICh9xhNRt+Y2DDKn6g3cc/TxHKy9aW7le0PLXw7eHws=@vger.kernel.org X-Gm-Message-State: AOJu0YyB+PkpfVgyxQ69R0DJvPTLQwv5OAPYYhuxfrUZWX/deoIraH49 skRdvQafBW5GobxiKpTREgaMRXjF59RXKw9oxhKtk/s3aHY44D+wUx2nx3V3J8j34Q/67Lw4vgh wTMkvpFVh0bdLEx8kUpJDO1s7+EbnUz8dHzE6rryWHySwrm23X5LeTz75ZCVm7AY3byx/scd1Hi E= X-Gm-Gg: AR+sD114tbRGc0SG3iOJvD2gHTpZR9S9siES67Z53qYfJwSTAPY5LgzWZESGtS4YT34 csbLTEllW6J62TGBUGJaJr0jQl5PlnLSRJqWy72ccNrFX8jsoGZrqSLqLMhsTBYp3QFUEBKLloB V5qzsQ2+KARELfvuuzJYQyh1XvalwH5aKC+vbafgAgrLqk68hE/dn6LBx5GcjWWu1NYiUrvkUEW V+PoicLcPw2NptojQWs9LRGGsIzB746BoJ4RuWDLK2NsuZoMd7Eqwgft6KljFkdLTFT8TjeoXf+ V94ddfkJuiK/v6LOaGpHHjV6RSzTqM1q3CChLw7Fa7WfoWdzibeovUwzKn2UZKhHcyDjuiCppVe jT7oOKcxUh5+p67ymQ8+B4l3D1lE3bNKXO681HExM2t5/ahQ/gwMAM3Avbv8VsnTCjj0gVKpFl4 IltqYum4VwBvPv+Q== X-Received: by 2002:a05:622a:1c09:b0:51c:7b12:5fe3 with SMTP id d75a77b69052e-5213f174546mr197315671cf.79.1784702191330; Tue, 21 Jul 2026 23:36:31 -0700 (PDT) X-Received: by 2002:a05:622a:1c09:b0:51c:7b12:5fe3 with SMTP id d75a77b69052e-5213f174546mr197315491cf.79.1784702190862; Tue, 21 Jul 2026 23:36:30 -0700 (PDT) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b2a9b8c6f6sm309696e87.4.2026.07.21.23.36.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jul 2026 23:36:29 -0700 (PDT) From: Dmitry Baryshkov Date: Wed, 22 Jul 2026 09:36:16 +0300 Subject: [PATCH 01/24] drm/msm/dp: reject YUV420-only modes without VSC SDP support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260722-drm-msm-display-interface-v1-1-368c10fe62fd@oss.qualcomm.com> References: <20260722-drm-msm-display-interface-v1-0-368c10fe62fd@oss.qualcomm.com> In-Reply-To: <20260722-drm-msm-display-interface-v1-0-368c10fe62fd@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5325; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=xwiwed+YWzAlxad0yWcCPqbevU3q9KR+updrF6TdV7A=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ1ZCyjPlhP1iD85plJTrXns08/XsY2v6mg54ifpFBKhMj OUXKg7vZDRmYWDkYpAVU2TxKWiZGrMpOezDjqn1MINYmUCmMHBxCsBEShnY/8oekhVL0L25MOy8 vGP+i/Q0/205sRxlVre/zRfoiA7btz9P/MO6mEc3f7LHGVa0513aacgnnlzH+sBvWvnv/WvFox1 9QxoctwodkNlZ6/uy5tCjvjD/SYe4xO9ITq9lPPRHZI9dRlbtqhiB1wW9xeeLS6bkzTHSX2CYbG fzPKTilYzvuUsa0f/39U/2TVU9dTJ1ideNFlWNy6V3dN8eDbUrfKTlpxTXyejtvlTfQ8Woeff/Q IZ5lZMP+LW6ytyVfi67OnWnTM65nQrcB9Km/ONcKS6+Zd57ZcVA5ulV+7fECnNu3pP8p48n4sYP O/3krpNuStdNJ/1fKxjfzFywe0UAd8DqJws7xTL+2FUAAA== X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: fBYJFqADRnTNZ1tAQVMOsEAwOxv6niER X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIyMDA1OSBTYWx0ZWRfXyYpx4NTnJ0eg vue4JJ9QUnOUpK4D/ZAfPch0Dj6sSpGtgK7QWRRpWySNRSeaHASCrJXFhe9+0vqT9rWxVOgIq5g bzOEtjZJY+kti0179G9BOciw/wDIaddCGIxbLgBQUCNg5lIbTeEQp7R79jxbv4npeNMA5Y76jt/ wexDg0kz14YB7E9kH8S1XOL6V5AxOYRkbw+3Vbcq2TYb0e+0GGkRj4L9wQcfNn3QSb2VV8fe5VO bLFcbJlMNiM1IdYc4LlPfToRYaC0LROIf7wv35QW04HCBzTeTsCgx0ezcNR4pe3f3+J/ar51YJs 3BApXabL2IX4hbksClFs2tVmrkBckzqIoUrjfSF4CDNhCHPNtLR0ljsFHpDiHkqnpH+84rP0w7e YHwDKAnJaIwdhMi+G6TsI9WjtYc4Q0DWifzYZb+ljWqEd1EwRx5dyDePchh3SJ9+vbtz7XUiLxP Pc1BhmVTfYTszog8XHQ== X-Authority-Analysis: v=2.4 cv=e/o2j6p/ c=1 sm=1 tr=0 ts=6a6064f0 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=zXqIQI19J2VV67nQZaQA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-ORIG-GUID: fBYJFqADRnTNZ1tAQVMOsEAwOxv6niER X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIyMDA1OSBTYWx0ZWRfXxCzyoZG4TnCa HD5xzju0MgGYNU/4Z7IkDOnZ7Zc4bPNoYSdbHCzGtP1wQJbZMhTvSE5jjXMtmRDpxf4SoqOBCGi OlBeAcAzVDjgK8HQrX4UrZMyu3wp2tI= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-22_02,2026-07-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607220059 DP conveys YUV 420 colorimetry through a VSC SDP. A sink that advertises a mode as YUV-420-only therefore cannot be driven at all unless the panel supports VSC SDP, yet msm_dp_bridge_mode_valid() only used the VSC SDP capability to decide whether to halve the pixel clock, otherwise letting such modes through to be validated (and possibly accepted) at the full RGB clock the sink cannot display. Reject 420-only modes with MODE_NO_420 when the panel does not support VSC SDP. With those modes filtered out, being a 420-only mode implies VSC SDP support, so the YUV-420 test reduces to drm_mode_is_420_only(): drop msm_dp_is_yuv_420_enabled() and call the DRM helper directly at its two callers (the DPU encoder already has the connector from the atomic state). Fixes: df9cf852ca30 ("drm/msm/dp: account for widebus and yuv420 during mode validation") Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +-- drivers/gpu/drm/msm/dp/dp_display.c | 28 ++++++++++++---------------- drivers/gpu/drm/msm/msm_drv.h | 8 -------- 3 files changed, 13 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 778e231d4967..1f20695f81e3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -710,8 +710,7 @@ void dpu_encoder_update_topology(struct drm_encoder *drm_enc, if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb))) topology->num_cdm++; } else if (disp_info->intf_type == INTF_DP) { - if (msm_dp_is_yuv_420_enabled(priv->kms->dp[disp_info->h_tile_instance[0]], - adj_mode)) + if (drm_mode_is_420_only(&connector->display_info, adj_mode)) topology->num_cdm++; } } diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index dc6f33809ca5..e0c44eef3aba 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -698,6 +698,7 @@ enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, u32 mode_rate_khz = 0, supported_rate_khz = 0, mode_bpp = 0; struct msm_dp *dp; int mode_pclk_khz = mode->clock; + bool is_yuv_420; dp = to_dp_bridge(bridge)->msm_dp_display; @@ -709,9 +710,16 @@ enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display); link_info = &msm_dp_display->panel->link_info; - if ((drm_mode_is_420_only(&dp->connector->display_info, mode) && - msm_dp_display->panel->vsc_sdp_supported) || - msm_dp_wide_bus_available(dp)) + is_yuv_420 = drm_mode_is_420_only(&dp->connector->display_info, mode); + + /* + * YUV 420 is carried over DP by signalling the colorimetry through a + * VSC SDP, so a 420-only mode cannot be driven without VSC SDP support. + */ + if (is_yuv_420 && !msm_dp_display->panel->vsc_sdp_supported) + return MODE_NO_420; + + if (is_yuv_420 || msm_dp_wide_bus_available(dp)) mode_pclk_khz /= 2; if (mode_pclk_khz > DP_MAX_PIXEL_CLK_KHZ) @@ -1277,22 +1285,10 @@ void __exit msm_dp_unregister(void) platform_driver_unregister(&msm_dp_display_driver); } -bool msm_dp_is_yuv_420_enabled(const struct msm_dp *msm_dp_display, - const struct drm_display_mode *mode) -{ - struct msm_dp_display_private *dp; - const struct drm_display_info *info; - - dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); - info = &msm_dp_display->connector->display_info; - - return dp->panel->vsc_sdp_supported && drm_mode_is_420_only(info, mode); -} - bool msm_dp_needs_periph_flush(const struct msm_dp *msm_dp_display, const struct drm_display_mode *mode) { - return msm_dp_is_yuv_420_enabled(msm_dp_display, mode); + return drm_mode_is_420_only(&msm_dp_display->connector->display_info, mode); } bool msm_dp_wide_bus_available(const struct msm_dp *msm_dp_display) diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 3787db8770ad..3d5679be488e 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -356,8 +356,6 @@ void __exit msm_dp_unregister(void); int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, struct drm_encoder *encoder, bool yuv_supported); void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); -bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, - const struct drm_display_mode *mode); bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, const struct drm_display_mode *mode); bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); @@ -382,12 +380,6 @@ static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm { } -static inline bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, - const struct drm_display_mode *mode) -{ - return false; -} - static inline bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, const struct drm_display_mode *mode) { -- 2.47.3