From: Zhi Wang <zhiw@nvidia.com>
To: <dakr@kernel.org>, <acourbot@nvidia.com>
Cc: <airlied@gmail.com>, <simona@ffwll.ch>, <ojeda@kernel.org>,
<alex.gaynor@gmail.com>, <boqun.feng@gmail.com>,
<gary@garyguo.net>, <bjorn3_gh@protonmail.com>,
<lossin@kernel.org>, <a.hindborg@kernel.org>,
<aliceryhl@google.com>, <tmgross@umich.edu>,
<jhubbard@nvidia.com>, <ecourtney@nvidia.com>,
<joelagnelf@nvidia.com>, <apopple@nvidia.com>, <cjia@nvidia.com>,
<smitra@nvidia.com>, <kjaju@nvidia.com>, <alkumar@nvidia.com>,
<ankita@nvidia.com>, <aniketa@nvidia.com>, <kwankhede@nvidia.com>,
<targupta@nvidia.com>, <nova-gpu@lists.linux.dev>,
<linux-kernel@vger.kernel.org>, <zhiwang@kernel.org>,
Zhi Wang <zhiw@nvidia.com>
Subject: [PATCH v5 5/6] gpu: nova-core: set RMSetSriovMode for vGPU
Date: Wed, 22 Jul 2026 10:39:12 +0300 [thread overview]
Message-ID: <20260722073913.1807677-6-zhiw@nvidia.com> (raw)
In-Reply-To: <20260722073913.1807677-1-zhiw@nvidia.com>
The GSP registry setup needs to advertise SR-IOV mode when nova-core boots
GSP for an enabled vGPU configuration. Without the registry entry, GSP-RM
is not told to initialize in the mode required by NVIDIA vGPU.
Append RMSetSriovMode to the SetRegistry command when the vGPU state
detected before GSP boot is enabled. Keep the existing registry entries
unchanged for non-vGPU boots.
Cc: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/gsp.rs | 1 -
drivers/gpu/nova-core/gsp/boot.rs | 2 +-
drivers/gpu/nova-core/gsp/commands.rs | 14 +++++++++++++-
drivers/gpu/nova-core/vgpu.rs | 1 -
4 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs
index 0480881d437f..70123dc54981 100644
--- a/drivers/gpu/nova-core/gsp.rs
+++ b/drivers/gpu/nova-core/gsp.rs
@@ -70,7 +70,6 @@ pub(crate) struct GspBootContext<'ctx, 'gpu> {
pub(crate) gsp_falcon: &'ctx Falcon<'gpu, GspFalcon>,
pub(crate) sec2_falcon: &'ctx Falcon<'gpu, Sec2Falcon>,
pub(crate) fsp: Option<&'ctx mut Fsp<'gpu>>,
- #[expect(dead_code)]
pub(crate) vgpu: &'ctx VgpuManager,
}
diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/boot.rs
index 6b7d00205000..a2e8342e7760 100644
--- a/drivers/gpu/nova-core/gsp/boot.rs
+++ b/drivers/gpu/nova-core/gsp/boot.rs
@@ -89,7 +89,7 @@ pub(crate) fn boot(
self.cmdq
.send_command_no_wait(bar, commands::SetSystemInfo::new(pdev, chipset))?;
self.cmdq
- .send_command_no_wait(bar, commands::SetRegistry::new()?)?;
+ .send_command_no_wait(bar, commands::SetRegistry::new(ctx.vgpu.state())?)?;
hal.post_boot(&self, ctx, &gsp_fw)?;
diff --git a/drivers/gpu/nova-core/gsp/commands.rs b/drivers/gpu/nova-core/gsp/commands.rs
index 08380de39048..134f34b19174 100644
--- a/drivers/gpu/nova-core/gsp/commands.rs
+++ b/drivers/gpu/nova-core/gsp/commands.rs
@@ -34,6 +34,7 @@
},
},
sbuffer::SBufferIter,
+ vgpu::VgpuState, //
};
/// The `GspSetSystemInfo` command.
@@ -72,7 +73,7 @@ pub(crate) struct SetRegistry {
impl SetRegistry {
/// Creates a new `SetRegistry` command, using a set of hardcoded entries.
- pub(crate) fn new() -> Result<Self> {
+ pub(crate) fn new(vgpu_state: VgpuState) -> Result<Self> {
let mut entries = KVec::new();
// RMSecBusResetEnable - enables PCI secondary bus reset
@@ -104,6 +105,17 @@ pub(crate) fn new() -> Result<Self> {
GFP_KERNEL,
)?;
+ if matches!(vgpu_state, VgpuState::Enabled { .. }) {
+ // RMSetSriovMode - required when vGPU is enabled.
+ entries.push(
+ RegistryEntry {
+ key: "RMSetSriovMode",
+ value: 1,
+ },
+ GFP_KERNEL,
+ )?;
+ }
+
Ok(Self { entries })
}
}
diff --git a/drivers/gpu/nova-core/vgpu.rs b/drivers/gpu/nova-core/vgpu.rs
index 71fd0fe879c2..5359847e2eb9 100644
--- a/drivers/gpu/nova-core/vgpu.rs
+++ b/drivers/gpu/nova-core/vgpu.rs
@@ -86,7 +86,6 @@ fn detect_state(
}
/// Returns the detected vGPU state for this boot.
- #[expect(dead_code)]
pub(crate) fn state(&self) -> VgpuState {
self.state
}
--
2.53.0
next prev parent reply other threads:[~2026-07-22 7:40 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-22 7:39 [PATCH v5 0/6] gpu: nova-core: boot GSP with vGPU enabled Zhi Wang
2026-07-22 7:39 ` [PATCH v5 1/6] PCI/IOV: Return unsigned int from pci_sriov_get_totalvfs() Zhi Wang
2026-07-22 7:39 ` [PATCH v5 2/6] rust: pci: add sriov_get_totalvfs() helper Zhi Wang
2026-07-23 5:30 ` Alexandre Courbot
2026-07-23 20:53 ` Danilo Krummrich
2026-07-22 7:39 ` [PATCH v5 3/6] gpu: nova-core: read vGPU mode from FSP via PRC protocol Zhi Wang
2026-07-22 7:39 ` [PATCH v5 4/6] gpu: nova-core: detect and store vGPU state Zhi Wang
2026-07-22 7:39 ` Zhi Wang [this message]
2026-07-22 7:52 ` [PATCH v5 5/6] gpu: nova-core: set RMSetSriovMode for vGPU sashiko-bot
2026-07-23 7:18 ` Alexandre Courbot
2026-07-23 8:49 ` Zhi Wang
2026-07-22 7:39 ` [PATCH v5 6/6] gpu: nova-core: reserve vGPU WPR2 heap Zhi Wang
2026-07-22 7:52 ` sashiko-bot
2026-07-23 7:23 ` Alexandre Courbot
2026-07-23 20:09 ` [PATCH v5 0/6] gpu: nova-core: boot GSP with vGPU enabled Danilo Krummrich
2026-07-24 7:26 ` Zhi Wang
2026-07-24 0:19 ` Alexandre Courbot
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