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Wed, 22 Jul 2026 07:24:10 -0700 (PDT) Received: from hu-mchunara-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3147dc7d8fbsm11231211eec.10.2026.07.22.07.24.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2026 07:24:10 -0700 (PDT) From: Monish Chunara X-Google-Original-From: Monish Chunara To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov Cc: Nitin Rawat , Pradeep Pragallapati , Komal Bajaj , Sachin Rathore , Monish Chunara , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio Subject: [PATCH V4 3/4] arm64: dts: qcom: Add SD Card support for Glymur SoC Date: Wed, 22 Jul 2026 19:53:41 +0530 Message-Id: <20260722142342.990384-4-mchunara@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260722142342.990384-1-mchunara@oss.qualcomm.com> References: <20260722142342.990384-1-mchunara@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIyMDE0MSBTYWx0ZWRfX7+tTbbe9lvST MsYQw4cmpd2TfutW2/j/c0Gj7mPm+IFkjVwXZZf/9DJXoHh8B0GcwpcBhlM4/h+A7mopUYofHWf HKxIshssGf+AtasQubauEZfpZyd2Rc0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIyMDE0MSBTYWx0ZWRfXxvm25EOqQkJQ 8cf0cPhfHCVou3dXRP5CLpfRwo10m3m0Ss7YHHpyewDXdk2kS8vw3kTxoIghBdmbY4ihUSxxHNx LUmfF8GFW7jARaSlyFc2xao2oFrT0bCxbVpldQLldRXPIJqqlBWu9FZ4ldjB0VJ8SDuOS1W0wbB xIq+m/4Rng7k+9PiHJGRUhPWQABQ4yy1gaLmXxDzVx+SOlFgWMytlkS6hXTS2XZGQg/LpARGGw3 I85C0SRIM1BPGvbI4Zr1NPkLFo4a0gjwv031r8cSDLSDG3khXBjeKXxz7UbQ01eRS4bdb/cOYX2 k7LXLPwTdiAm/zSLFdkGlDud1Z01wEyPg4TTMKL3j+l7pKs4j0zzf7NUADFMfUMSGkOfggC2gqd p7YU11IeryDfU6/mvDvxqxiVhMMhZw7OHoMOeLQRXIutk0aqfseNsbE1tMNOULqmRP3xNcLjyyk b3paw/x/mE0zaZRqPdw== X-Authority-Analysis: v=2.4 cv=Rsv16imK c=1 sm=1 tr=0 ts=6a60d28d cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=9wC1NwHXjCwt_iaUHW8A:9 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: 7qELNenjeusW45YoKxI_QhfIsH1uaGqR X-Proofpoint-ORIG-GUID: 7qELNenjeusW45YoKxI_QhfIsH1uaGqR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-22_04,2026-07-22_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 phishscore=0 spamscore=0 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607220141 From: Monish Chunara Add support for SD card on Glymur SoC and enable the required pinctrl configurations. Co-developed-by: Sachin Rathore Signed-off-by: Sachin Rathore Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Monish Chunara --- arch/arm64/boot/dts/qcom/glymur.dtsi | 91 ++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 55d91c696a3a..e7eb710aa743 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4444,6 +4444,58 @@ lpass_ag_noc: interconnect@7e40000 { #interconnect-cells = <2>; }; + sdhc_2: mmc@8804000 { + compatible = "qcom,glymur-sdhci", "qcom,sdhci-msm-v5"; + + reg = <0x0 0x08804000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + iommus = <&apps_smmu 0xd00 0x0>; + qcom,dll-config = <0x0007442c>; + qcom,ddr-config = <0x80040868>; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + interconnects = <&aggre3_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + bus-width = <4>; + dma-coherent; + + resets = <&gcc GCC_SDCC2_BCR>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + usb_2_hsphy: phy@88e0000 { compatible = "qcom,glymur-m31-eusb2-phy", "qcom,sm8750-m31-eusb2-phy"; @@ -6264,6 +6316,45 @@ rx-pins { bias-disable; }; }; + sdc2_default_state: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_sleep_state: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; stm: stm@10002000 { -- 2.34.1