[PATCH v2] PCI: Fix 32-bit config write in Intel RP MPC ACS quirk

[Mohamad Raizudeen <raizudeen.kerneldev@gmail.com>]

The pci_quirk_enable_intel_rp_mpc_acs() reads a 32 bit DWORD from the
MPC register, sets bit 26 (INTEL_MPC_REG_IRBNCE), but it writes it back
using pci_write_config_word().

Because bit 26 resides in the upper 16 bits of the 32 bit register, a 16
bit write to offset 0xd8 completely drops the newly set bit. The quirk
logs that it is enabling IRBNCE, but the hardware never actually
receives the command.

Fix this by using pci_write_config_dword() to ensure the full 32 bit
value is written back to the hardware.

Fixes: d99321b63b1f ("PCI: Enable quirks for PCIe ACS on Intel PCH root ports")
Signed-off-by: Mohamad Raizudeen <raizudeen.kerneldev@gmail.com>
---
Changes in v2:
- Added "Fixes:" tag and CC'd Alex Williamson as requested by Bjorn Helgaas.

Link to v1: https://lore.kernel.org/linux-pci/20260723160641.GC836122@bhelgaas/T/#t

 drivers/pci/quirks.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index b09f27f7846f..0d0cf6f86173 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5361,7 +5361,7 @@ static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
 	if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
 		pci_info(dev, "Enabling MPC IRBNCE\n");
 		mpc |= INTEL_MPC_REG_IRBNCE;
-		pci_write_config_word(dev, INTEL_MPC_REG, mpc);
+		pci_write_config_dword(dev, INTEL_MPC_REG, mpc);
 	}
 }
 
-- 
2.53.0