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Fri, 24 Jul 2026 20:19:15 -0700 (PDT) From: Cody Kang Date: Fri, 24 Jul 2026 23:16:46 -0400 Subject: [PATCH 14/17] riscv: dts: spacemit: k3: add display nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260724-k3-display-v1-14-f22a10a52867@gmail.com> References: <20260724-k3-display-v1-0-f22a10a52867@gmail.com> In-Reply-To: <20260724-k3-display-v1-0-f22a10a52867@gmail.com> To: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Vinod Koul , Neil Armstrong , Haylen Chu , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, Cody Kang X-Mailer: b4 0.15.1 Add the SoC-level display nodes: the two Saturn DPUs, the two DP/eDP controllers with their PHY children. The PHY PLLs are fed back into the APMU as pixel-clock mux parents, so updated the &syscon_apmu node in the display dtsi. Signed-off-by: Cody Kang --- arch/riscv/boot/dts/spacemit/k3-display.dtsi | 156 +++++++++++++++++++++++++++ 1 file changed, 156 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-display.dtsi b/arch/riscv/boot/dts/spacemit/k3-display.dtsi new file mode 100644 index 000000000000..4892ee6acda2 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3-display.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * SpacemiT K3 display subsystem (DPU0/eDP0 + DPU1/DP1) shared + * device-tree definitions for inclusion alongside k3.dtsi. + * + * Copyright (C) 2026 SpacemiT Co., Ltd. + */ + +#include +#include +#include + +&soc { + dpu0_crtc0: dpu@c0340000 { + compatible = "spacemit,k3-saturn-dpu"; + reg = <0x0 0xc0340000 0x0 0x54000>; + interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, + <89 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "online", "offline"; + clocks = <&syscon_apmu CLK_APMU_LCD_PXCLK>, + <&syscon_apmu CLK_APMU_LCD_MCLK>, + <&syscon_apmu CLK_APMU_DPU_ACLK>, + <&syscon_apmu CLK_APMU_DSI_ESC>, + <&syscon_apmu CLK_APMU_LCD_DSC>; + clock-names = "pxclk", "mclk", "aclk", "escclk", "dscclk"; + resets = <&syscon_apmu RESET_APMU_LCD_MCLK>, + <&syscon_apmu RESET_APMU_LCD>, + <&syscon_apmu RESET_APMU_DSI_ESC>, + <&syscon_apmu RESET_APMU_DPU_ACLK>, + <&syscon_apmu RESET_APMU_LCD_DSCCLK>; + reset-names = "mclk", "lcd", "esc", + "aclk", "dsc"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu0_out: endpoint { + remote-endpoint = <&edp0_in>; + }; + }; + }; + }; + + edp0: edp@cac84000 { + compatible = "spacemit,k3-inno-dp"; + reg = <0x0 0xcac84000 0x0 0x4000>; + interrupts = <132 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apmu CLK_APMU_EDP0_PXCLK>, <&edp0_phy>; + clock-names = "pxclk", "pll"; + resets = <&syscon_apmu RESET_APMU_EDP0>; + phys = <&edp0_phy>; + phy-names = "dp"; + status = "disabled"; + + edp0_phy: phy { + compatible = "spacemit,k3-inno-dp-phy"; + #phy-cells = <0>; + #clock-cells = <0>; + clock-output-names = "edp0_pll_pxclk"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + edp0_in: endpoint { + remote-endpoint = <&dpu0_out>; + }; + }; + /* port@1 (panel output) is added by boards fitting an eDP panel */ + }; + }; + + dpu1_crtc0: dpu@c0440000 { + compatible = "spacemit,k3-saturn-dpu"; + reg = <0x0 0xc0440000 0x0 0x54000>; + interrupts = <139 IRQ_TYPE_LEVEL_HIGH>, + <138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "online", "offline"; + clocks = <&syscon_apmu CLK_APMU_DSI4LN2_LCD_PXCLK>, + <&syscon_apmu CLK_APMU_DSI4LN2_LCD_MCLK>, + <&syscon_apmu CLK_APMU_DSI4LN2_DPU_ACLK>, + <&syscon_apmu CLK_APMU_DSI4LN2_DSI_ESC>, + <&syscon_apmu CLK_APMU_DSI4LN2_LCD_DSC>; + clock-names = "pxclk", "mclk", "aclk", "escclk", "dscclk"; + resets = <&syscon_apmu RESET_APMU_DSI4LN2_LCD_MCLK>, + <&syscon_apmu RESET_APMU_DSI4LN2_LCD_SW>, + <&syscon_apmu RESET_APMU_DSI4LN2_ESCCLK>, + <&syscon_apmu RESET_APMU_DSI4LN2_DPU_ACLK>, + <&syscon_apmu RESET_APMU_DSI4LN2_LCD_DSCCLK>; + reset-names = "mclk", "lcd", "esc", + "aclk", "dsc"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu1_out: endpoint { + remote-endpoint = <&dp1_in>; + }; + }; + }; + }; + + dp1: dp@cac88000 { + compatible = "spacemit,k3-inno-dp"; + reg = <0x0 0xcac88000 0x0 0x4000>; + interrupts = <140 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon_apmu CLK_APMU_EDP1_PXCLK>, <&dp1_phy>; + clock-names = "pxclk", "pll"; + resets = <&syscon_apmu RESET_APMU_EDP1>; + phys = <&dp1_phy>; + phy-names = "dp"; + status = "disabled"; + + dp1_phy: phy { + compatible = "spacemit,k3-inno-dp-phy"; + #phy-cells = <0>; + #clock-cells = <0>; + clock-output-names = "edp1_pll_pxclk"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp1_in: endpoint { + remote-endpoint = <&dpu1_out>; + }; + }; + /* no port@1: the DP TX drives the external connector directly */ + }; + }; +}; + +/* + * Feed the PHY PLL pixel clocks back in as the APMU mux parents. This lives + * here, not in k3.dtsi: the PHYs only exist where this file is included. + */ +&syscon_apmu { + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>, + <&edp0_phy>, <&dp1_phy>; + clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m", + "edp0_pll_pxclk", "edp1_pll_pxclk"; +}; -- 2.43.0