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Fri, 24 Jul 2026 20:17:26 -0700 (PDT) From: Cody Kang Date: Fri, 24 Jul 2026 23:16:34 -0400 Subject: [PATCH 02/17] dt-bindings: phy: add SpacemiT K3 Innosilicon DP PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260724-k3-display-v1-2-f22a10a52867@gmail.com> References: <20260724-k3-display-v1-0-f22a10a52867@gmail.com> In-Reply-To: <20260724-k3-display-v1-0-f22a10a52867@gmail.com> To: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Vinod Koul , Neil Armstrong , Haylen Chu , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, Cody Kang X-Mailer: b4 0.15.1 The SpacemiT K3 DisplayPort controller drives its four transmit lanes through an integrated Innosilicon DP PHY, one PHY per controller. Add a binding so the controller can reference its transmit PHY and the pixel clock the PHY's PLL sources. The PHY's registers are interleaved with its parent controller's inside one MMIO window, so it owns neither a reg nor a reset and is modelled as a child of the controller. It exposes its PLL-generated pixel clock through #clock-cells, so the APMU pixel-clock mux can select it as a parent through the clock framework. Signed-off-by: Cody Kang --- .../bindings/phy/spacemit,k3-inno-dp-phy.yaml | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/spacemit,k3-inno-dp-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k3-inno-dp-phy.yaml new file mode 100644 index 000000000000..f8f1ef372951 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/spacemit,k3-inno-dp-phy.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/spacemit,k3-inno-dp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K3 Innosilicon DisplayPort PHY + +maintainers: + - Cody Kang + +description: + Innosilicon four-lane DisplayPort transmit PHY integrated in the SpacemiT + K3 SoC, one per DisplayPort controller. Its registers are interleaved with + the controller's own inside a single register window, so it is described as + a child of the controller and owns neither a reg nor a reset. + + The PHY provides the pixel clock its PLL generates, which the APMU + pixel-clock mux takes as one of its inputs. + +properties: + compatible: + const: spacemit,k3-inno-dp-phy + + "#phy-cells": + const: 0 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - "#phy-cells" + - "#clock-cells" + +additionalProperties: false + +examples: + - | + phy { + compatible = "spacemit,k3-inno-dp-phy"; + #phy-cells = <0>; + #clock-cells = <0>; + clock-output-names = "edp0_pll_pxclk"; + }; -- 2.43.0