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Fri, 24 Jul 2026 20:18:01 -0700 (PDT) From: Cody Kang Date: Fri, 24 Jul 2026 23:16:38 -0400 Subject: [PATCH 06/17] clk: spacemit: k3: parent eDP/DP pixel clock to the PHY PLL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260724-k3-display-v1-6-f22a10a52867@gmail.com> References: <20260724-k3-display-v1-0-f22a10a52867@gmail.com> In-Reply-To: <20260724-k3-display-v1-0-f22a10a52867@gmail.com> To: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Vinod Koul , Neil Armstrong , Haylen Chu , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, Cody Kang X-Mailer: b4 0.15.1 The APMU eDP/DP pixel-clock muxes were parented to a placeholder, because their real parents (the DP PHY PLLs) did not exist as clocks yet. They do now, so point each mux at its PLL and let the pixel clock reach the controller through the clock framework. Signed-off-by: Cody Kang --- drivers/clk/spacemit/ccu-k3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c index cb0c4277f72a..afbbbd797826 100644 --- a/drivers/clk/spacemit/ccu-k3.c +++ b/drivers/clk/spacemit/ccu-k3.c @@ -937,13 +937,13 @@ CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, static const struct clk_parent_data edp0_pclk_parents[] = { CCU_PARENT_HW(lcd_pxclk), - CCU_PARENT_NAME(external_clk), + CCU_PARENT_NAME(edp0_pll_pxclk), }; CCU_MUX_GATE_DEFINE(edp0_pxclk, edp0_pclk_parents, APMU_LCD_EDP_CTRL, 2, 1, BIT(1), 0); static const struct clk_parent_data edp1_pclk_parents[] = { CCU_PARENT_HW(dsi4ln2_lcd_pxclk), - CCU_PARENT_NAME(external_clk), + CCU_PARENT_NAME(edp1_pll_pxclk), }; CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0); -- 2.43.0