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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38f03b0e976sm647015a91.5.2026.07.23.18.41.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 18:41:39 -0700 (PDT) From: Joey Lu To: mturquette@baylibre.com, sboyd@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v5 0/3] clk: nuvoton: ma35d1: fix PLL frequency calculation Date: Fri, 24 Jul 2026 09:40:36 +0800 Message-ID: <20260724014039.1239552-1-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Fix four bugs in the MA35D1 PLL clock driver that cause incorrect frequency values returned from recalc_rate() and determine_rate(). v1 combined all fixes into a single commit. At reviewer request, split into one patch per logical fix: 1/3 - fix div_u64 return value being discarded (affects both ma35d1_calc_smic_pll_freq and ma35d1_calc_pll_freq INT mode) 2/3 - fix PLL_CTL1_FRAC mask width (8-bit -> 24-bit) and update the fractional-mode arithmetic accordingly 3/3 - fix ma35d1_clk_pll_determine_rate: move find_closest() into the configurable-PLL branch; split CAPLL and DDRPLL into separate case labels mirroring recalc_rate() Changes in v5 (vs v4): - 3/3: split CAPLL and DDRPLL back into separate case labels so that determine_rate() is structurally parallel with recalc_rate(); add explicit default label; share single req->rate = pll_freq tail (readability suggestion by Alexandre Mergnat) - 3/3: add Reviewed-by tag Changes in v4 (vs v3): - 2/3: add Reviewed-by tag Changes in v3 (vs v2): - 2/3: replace the manual round-to-nearest expression "(u32)(((u64)x * 1000 + 500) >> 24)" with the kernel helper DIV_ROUND_CLOSEST_ULL((u64)x * 1000, 1ULL << 24); the result is mathematically identical but more readable and idiomatic Joey Lu (3): clk: nuvoton: ma35d1: fix ignored div_u64 return values in PLL freq calculation clk: nuvoton: ma35d1: fix PLL_CTL1_FRAC bit field width and fractional calc clk: nuvoton: ma35d1: fix ma35d1_clk_pll_determine_rate logic drivers/clk/nuvoton/clk-ma35d1-pll.c | 43 ++++++++++++++-------------- 1 file changed, 22 insertions(+), 21 deletions(-) -- 2.43.0