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It uses separate SDMCLK (CIU) and L4_MP (BIU) clocks, and has three resets for the host controller, Combo PHY, and SDMMC OCP bridge. On the SOCDK OOBE card the slot is SD-only: fixed 3.3 V card supply and a GPIO-selected 3.3 V / 1.8 V I/O supply for UHS-I signalling up to SDR104. Signed-off-by: Tanmay Kathpalia --- Depends on commit ab45ecfab540 ("dt-bindings: reset: altr: add COMBOPHY_RESET for Agilex5"), which is already in mainline via the reset tree. It is not yet in mmc/next; apply or merge that commit when building/testing this patch on top of mmc/next. .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 25 ++++++++++++ .../boot/dts/intel/socfpga_agilex5_socdk.dts | 38 ++++++++++++++++++- 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index b06c6d5d60ee..5ccbd7bf2034 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -300,6 +300,31 @@ portb: gpio-controller@0 { }; }; + /* + * Shared SD/eMMC controller node. On the SOCDK OOBE daughter-card + * this is used for SD card operation; on the SOCDK eMMC daughter-card + * it is configured for eMMC. + */ + emmc: mmc@10808000 { + compatible = "altr,agilex5-sd6hc", "cdns,sd6hc"; + reg = <0x10808000 0x1000>; + /* + * "ciu" (SDMCLK) is listed first so it is selected as the + * primary clock by the SDHCI platform layer; the SD6HC PHY + * timing calculations are derived from this clock rate. + */ + clocks = <&clkmgr AGILEX5_SDMCLK>, <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names = "ciu", "biu"; + dma-coherent; + interrupts = ; + iommus = <&smmu 5>; + resets = <&rst SDMMC_RESET>, <&rst COMBOPHY_RESET>, + <&rst SDMMC_OCP_RESET>; + reset-names = "sdhc-reset", "combophy", "sdmmc-ocp"; + + status = "disabled"; + }; + nand: nand-controller@10b80000 { compatible = "cdns,hp-nfc"; reg = <0x10b80000 0x10000>, diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts index 57d3c5807c65..f37038066922 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -36,9 +36,37 @@ memory@80000000 { /* We expect the bootloader to fill in the reg */ reg = <0x0 0x80000000 0x0 0x0>; }; + + vqmmc_io_reg: regulator-1p8v { + compatible = "regulator-gpio"; + gpios = <&portb 3 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vqmmc-io"; + states = <1800000 0x1>, + <3300000 0x0>; + }; + + vmmc_reg: regulator-fixed-3p3v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc-sd"; + }; }; -&gpio0 { +&emmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vmmc_reg>; + vqmmc-supply = <&vqmmc_io_reg>; + status = "okay"; }; @@ -59,6 +87,10 @@ emac2_phy0: ethernet-phy@0 { }; }; +&gpio0 { + status = "okay"; +}; + &gpio1 { status = "okay"; }; @@ -100,6 +132,10 @@ root: partition@4200000 { }; }; +&smmu { + status = "okay"; +}; + &uart0 { status = "okay"; }; -- 2.43.7