From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD4513B19A3 for ; Sat, 25 Jul 2026 16:25:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784996711; cv=none; b=LQRa4Y78Ax8KpTwP7iKwf4zCwz/bF4S/+8i8serNx9VzocjSC7IQeJdq6DStRkAEng55yNaZwxrEHlMod00Iy7oqV7fTZigUyQrawabt/Eotl0j/deZVGlqifWREofwJH2V4odOzRA2t52V/2rNRJpWyCQUhRwbojffhU1BBFo8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784996711; c=relaxed/simple; bh=r2JJHgXhwc1ADtCHrGf0UlVCwtW1fHav/6tv4ES6/a4=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=kKe4vvCLEKKEVb0hATIZJaZYAmBbL8HyoEDxnMe/zwvZhbuk5fuFPS1wUETXar0IjiqRSwmjR4ois1pD9ZqtDaJOgCqtz0+RwP1UPpuTU45oF3G/1rLbUp21HX6dbIVSfRA1sVh2I1nhRrhuSHTuuBWKzIFF5JyA6/2BezodX0E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Nv1xG+eo; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Nv1xG+eo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5AE231F000E9; Sat, 25 Jul 2026 16:25:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784996709; bh=eXdq8pjz28evqcBzIPG2oZHIuqFHhx8mdctRki8jLvw=; h=From:To:Cc:Subject:Date; b=Nv1xG+eoDJ33ZiTxB2Q+MtkSfhTS0Utuw2iSHxEA0VvNABS6YdkDD2eooM2YUPaJx FSXRMzfi39rQV9PTjU8HkbsyRNKHcNYD5OZ1H1MS1rmscprx9pz2M/j9t2DVtLDNA5 D7iUVFVd3BHZgey+uXnBIGQs2X1wi+V3Dx0HuD8MBZ/Ce5w0OFSfmPT2yt2URLtr87 lPiAEJfzch2oxME/0vrApVM0ViiqA4059/66amDBdZpKud1IGkV/f3mOnBTN1n00dO 1IdHOuiJGfhd/6ByS3UGyqD9GHfrbbffKg7oL+xk6Z059WWkkjVVKFr4TaUdIMgDqV mQRRkIl6+6Gyw== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wnfBT-00000008nT1-1n4n; Sat, 25 Jul 2026 16:25:07 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Rutland , Will Deacon Subject: [PATCH] perf: arm_pmu_acpi: Get rid of the edge-triggered interrupt oddity Date: Sat, 25 Jul 2026 17:26:27 +0100 Message-ID: <20260725162627.145301-1-maz@kernel.org> X-Mailer: git-send-email 2.47.3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mark.rutland@arm.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false The ACPI spec bizarrely indicates that the PMU interrupt can be edge-triggered, which contradicts the very basics of the PMU architecture (SW is required to clear the interrupt condition for the level to drop). Remove the code parsing this flag and always flag the interrupt as level triggered, no matter what firmware says. Signed-off-by: Marc Zyngier --- drivers/perf/arm_pmu_acpi.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c index e80f76d95e68b..ca6bf8f86cfe9 100644 --- a/drivers/perf/arm_pmu_acpi.c +++ b/drivers/perf/arm_pmu_acpi.c @@ -22,7 +22,7 @@ static DEFINE_PER_CPU(int, pmu_irqs); static int arm_pmu_acpi_register_irq(int cpu) { struct acpi_madt_generic_interrupt *gicc; - int gsi, trigger; + int gsi; gicc = acpi_cpu_get_madt_gicc(cpu); @@ -38,11 +38,6 @@ static int arm_pmu_acpi_register_irq(int cpu) if (!gsi) return 0; - if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE) - trigger = ACPI_EDGE_SENSITIVE; - else - trigger = ACPI_LEVEL_SENSITIVE; - /* * Helpfully, the MADT GICC doesn't have a polarity flag for the * "performance interrupt". Luckily, on compliant GICs the polarity is @@ -53,8 +48,12 @@ static int arm_pmu_acpi_register_irq(int cpu) * may not match the real polarity, but that should not matter. * * Other interrupt controllers are not supported with ACPI. + * + * The spec also indicates that the PMU interrupt can be edge + * triggered, which doesn't make any sense (SW needs to clear the + * interrupt condition for the level to drop). Ignore the silly flag. */ - return acpi_register_gsi(NULL, gsi, trigger, ACPI_ACTIVE_HIGH); + return acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH); } static void arm_pmu_acpi_unregister_irq(int cpu) -- 2.47.3