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Mon, 27 Jul 2026 02:21:35 -0700 (PDT) Received: from QCOM-eG0v1AUPpu.na.qualcomm.com ([2a01:e0a:830:450:61cd:dcd3:c61a:ac3c]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69fb51c9babsm2265326a12.12.2026.07.27.02.21.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jul 2026 02:21:34 -0700 (PDT) From: Loic Poulain Subject: [PATCH v2 0/3] i2c: qcom-cci: Fix CCI clock rate enforcement Date: Mon, 27 Jul 2026 11:21:31 +0200 Message-Id: <20260727-cci-clk-fix-v2-0-c3958f28b045@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIABsjZ2oC/22MQQ6CMBBFr0Jm7ZC2EUtceQ/DopZBJgLVVhsN6 d0dWbv5yXvJfyskikwJjtUKkTInDouA2VXgR7dcCbkXBqPMQVmj0XtGP91w4DcOpPfNxTg/OAv yuEcSvdXOnfDI6RniZ4tn/bP/O1mjwoYc2dYq1bv2FFKqHy83+TDPtQx0pZQvju67Hq0AAAA= X-Change-ID: 20260721-cci-clk-fix-fe145b2acfa7 To: Robert Foss , Andi Shyti , Wolfram Sang , Dmitry Baryshkov , Luca Weiss Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, vladimir.zapolskiy@linaro.org, Loic Poulain , Wenmeng Liu , Konrad Dybcio X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI3MDA5MSBTYWx0ZWRfX4adA0c7ksLOK ACN2vfQpQf1lXnbuGNAu7KF2EaFz/9vbR9E8LRK8eRj+6kj15N2zKAWKNQjzFcfHFZcPrOpNjK0 HjBA1IgKt9KvLhluua3LQBVNNLQZFEMD6o/VDW1NfTQ6SdZ0lbTWUCuU9ad0OxHHGsZTgPnhL3n rBRvMiKlm+cPLVj+8PGj98NeUX/MUauC1jZ8hnMfwm1gnRbOI0KqLcKCb2gOJaUW7oBrhoNUMm0 uvyag8qSlGYvJ5ruPts2j3nIv0NeyNxk/zH6e9SIxNqUYNo9p2WYk5785Sg7Xx6QsShYgrunn/w 7ACgjEAIOAsYF1xMsfG6Ji3aaJ0VA3QvIHQeaL/VQQHNk8KEsyfPhZZsEzzA2TSu3+0CLYCikPE hL94o9gGw5KF7dYwzGgD+wm9t4RvPkZvOKpXRc8UF7JkmSs+pQd5jbUzyV1w3l1asIxOYh0sauQ PapbRpv5UiUcNhq+1Ng== X-Authority-Analysis: v=2.4 cv=UPbt2ify c=1 sm=1 tr=0 ts=6a672320 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=GMDCHhIFIY8WwY_rtYAA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI3MDA5MSBTYWx0ZWRfX98bLTUDSKoQK Ijx04RwSQI5Pgo6Y9pDYP1zh3BJvTtmC7lvxFCAHF1JK/ZvRIJuWQJOG4FIsVulNKlGzNxaycBO JisNT803oGbimdK3ArNxn6Iju/wjVxQ= X-Proofpoint-ORIG-GUID: 8BIQBSjl_ghxNh3HAcbzZULj_JzQ0jrl X-Proofpoint-GUID: 8BIQBSjl_ghxNh3HAcbzZULj_JzQ0jrl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-27_02,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 bulkscore=0 clxscore=1015 spamscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607270091 The CCI hw_params timing values (thigh, tlow, etc.) are expressed in clock ticks and were calibrated for a specific CCI clock frequency per hardware variant (19.2 MHz for v1/v1.5, 37.5 MHz for v2). Running at the wrong frequency causes incorrect I2C timings that may violate the I2C specification. A previous series removed the cci_clk_rate field and the associated warning from the driver on the grounds that the warning was noisy and the rate was already set via assigned-clock-rates in the DT. However, enforcing a clock frequency configuration through DT is fragile and not the right approach, the driver owns the hw_params and should own the clock rate too. This series first fixes the msm8953 timing table, which is internally inconsistent (Standard/Fast calibrated for 19.2 MHz but Fast+ for 37.5 MHz), by reusing the v2 config (same hardware version as msm8996/sdm630). It then reverts the removal of cci_clk_rate and replaces the passive warn-only approach with an active rate enforcement at probe time. The rate is applied through the OPP framework so that boards describing an opp table also get the required power-domain and regulator votes. Note: Vladimir suggested selecting the CCI clock rate per I2C mode (Standard/Fast/Fast+) rather than a single per-variant rate. That would be a much larger change as it requires a table describing all the rates supported for a given clock, plus proper vote/arbitration management, since a single CCI clock is shared by multiple masters that may run in different modes simultaneously. So this is out of scope for this series, which keeps the simpler per-variant rate. Signed-off-by: Loic Poulain --- Changes in v2: - Instead of adding a 19.2 MHz cci_clk_rate for msm8953, switch it to the v2 config (37.5 MHz). The msm8953 table was internally inconsistent (Standard/Fast for 19.2 MHz, Fast+ for 37.5 MHz), so a single rate could not satisfy all modes. msm8953 is the same HW version as msm8996/sdm630, which already use v2. (Vladimir) - Remove the msm8953 fix tag (Vladimir) - Apply the rate via the OPP framework instead of a bare clk_set_rate(), managing the vote across runtime PM. (Konrad) - Link to v1: https://lore.kernel.org/r/20260721-cci-clk-fix-v1-0-5eae78700da8@oss.qualcomm.com --- Loic Poulain (3): i2c: qcom-cci: Switch msm8953 to the CCI v2 timing/rate config Revert "i2c: qcom-cci: Remove unused struct member cci_clk_rate" i2c: qcom-cci: Fix CCI clock rate enforcement drivers/i2c/busses/i2c-qcom-cci.c | 100 ++++++++++++++++++++------------------ 1 file changed, 54 insertions(+), 46 deletions(-) --- base-commit: fce2dfa773ced15f27dd27cd0b482a7473cdcf2a change-id: 20260721-cci-clk-fix-fe145b2acfa7 Best regards, -- Loic Poulain