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Mon, 27 Jul 2026 02:21:40 -0700 (PDT) X-Received: by 2002:a05:622a:144b:b0:526:d946:fc15 with SMTP id d75a77b69052e-529cce5f011mr480911cf.66.1785144099861; Mon, 27 Jul 2026 02:21:39 -0700 (PDT) Received: from QCOM-eG0v1AUPpu.na.qualcomm.com ([2a01:e0a:830:450:61cd:dcd3:c61a:ac3c]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69fb51c9babsm2265326a12.12.2026.07.27.02.21.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jul 2026 02:21:39 -0700 (PDT) From: Loic Poulain Date: Mon, 27 Jul 2026 11:21:34 +0200 Subject: [PATCH v2 3/3] i2c: qcom-cci: Fix CCI clock rate enforcement Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260727-cci-clk-fix-v2-3-c3958f28b045@oss.qualcomm.com> References: <20260727-cci-clk-fix-v2-0-c3958f28b045@oss.qualcomm.com> In-Reply-To: <20260727-cci-clk-fix-v2-0-c3958f28b045@oss.qualcomm.com> To: Robert Foss , Andi Shyti , Wolfram Sang , Dmitry Baryshkov , Luca Weiss Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, vladimir.zapolskiy@linaro.org, Loic Poulain , Wenmeng Liu , Konrad Dybcio X-Mailer: b4 0.14.2 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI3MDA5MiBTYWx0ZWRfX5rQPbRvY7S8M veJP9T2ceGCvcKGxIvC/A0oxfqVYbue8RqzUKy5quhNVtRQG1cW9nHWFKyQ2UC0nCOgU6OIbl7i ZdK3nGBEa6Q4SZB6jZwwn/ot+bxFAAU= X-Authority-Analysis: v=2.4 cv=UYBhjqSN c=1 sm=1 tr=0 ts=6a672325 cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=XlnqjZJP-Q2boqhwfUgA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-GUID: 6qZq4SeORdM1m3-RITJ7xyKouf82RZLD X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI3MDA5MiBTYWx0ZWRfXwmdcI2P8Pq8A w6l2iztYzjCUitmUHSoJRgNgDWE/VB0Nx1Sh3IAnkMnjGNhnyOru5qPPW780sGKlqd1fdW6te7J gLDc1C9TH7LdD6RgXJ+GHbu1QeG1vQXgIIlkFYvhrkimnnN/bP6xrF2ujEiyxVkHa2eqwoIfzfF CQioCK7DpR1DpS7akoXHfPjslko15IQsed8G66P+F5Umi7f677FSdqVsxwL1yNJYSiTCHmMM0jP j2y2ZF41Xzk99qKsA7bjGVJXaLrurwpo9a8lWol9eMGSIXUogFtUI6xRIUrpwpDUHMZ7AsOaiXK Wav33h+bW7SC7oVwIvXOizjTuQ+YBzlZkifSceV28Wcp5Uy9DtLwIFFcdjSDf7dFX4KmHqueJ0F AMLTkSyR5gACJGug2ylYIIle4P9c2JnDmv+shK1/YI2CqWMaBhcJJAAc1hYZWKcZCJ0RAUmVeGU oWTY6JA7BaKx3rHz9/w== X-Proofpoint-ORIG-GUID: 6qZq4SeORdM1m3-RITJ7xyKouf82RZLD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-27_02,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 phishscore=0 adultscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607270092 The hw_params timing values (thigh, tlow, etc.) are in CCI clock ticks and were calibrated for a specific clock rate per hardware variant. If the clock is running at a different rate the I2C timings will be wrong, potentially violating the I2C specification. Rather than just warning about a mismatch like before, actively set the clock to the expected rate, using the OPP framework so that boards which (will) describe an opp table also get the required power-domain and regulator votes for that rate. The OPP table is optional, boards without one simply fall back to a plain clk_set_rate() behavior, so existing DTs keep working. Tested-by: Wenmeng Liu Suggested-by: Konrad Dybcio Signed-off-by: Loic Poulain --- drivers/i2c/busses/i2c-qcom-cci.c | 49 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c index 2ed58b2a2f31c62ee1c972a53b71f86787144b84..87d64e308a8152b99ff4cfb4255e24edfb751e75 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -11,6 +11,7 @@ #include #include #include +#include #define CCI_HW_VERSION 0x0 #define CCI_RESET_CMD 0x004 @@ -128,6 +129,7 @@ struct cci { const struct cci_data *data; struct clk_bulk_data *clocks; int nclocks; + struct clk *cci_clk; struct cci_master master[NUM_MASTERS]; }; @@ -472,10 +474,35 @@ static void cci_disable_clocks(struct cci *cci) clk_bulk_disable_unprepare(cci->nclocks, cci->clocks); } +static int cci_set_core_rate(struct cci *cci, unsigned long rate) +{ + struct device *dev = cci->dev; + int ret; + + ret = dev_pm_opp_set_rate(dev, rate); + if (ret) { + dev_warn(dev, "CCI clock could not be set to %lu Hz\n", rate); + return ret; + } + + if (!rate) + return 0; + + /* + * The hw_params timings are only valid at the expected rate, + * so verify what actually landed on the hardware. + */ + if (clk_get_rate(cci->cci_clk) != rate) + dev_warn(dev, "CCI clock is not at expected %lu Hz\n", rate); + + return 0; +} + static int __maybe_unused cci_suspend_runtime(struct device *dev) { struct cci *cci = dev_get_drvdata(dev); + cci_set_core_rate(cci, 0); cci_disable_clocks(cci); return 0; } @@ -485,6 +512,10 @@ static int __maybe_unused cci_resume_runtime(struct device *dev) struct cci *cci = dev_get_drvdata(dev); int ret; + ret = cci_set_core_rate(cci, cci->data->cci_clk_rate); + if (ret) + return ret; + ret = cci_enable_clocks(cci); if (ret) return ret; @@ -587,6 +618,24 @@ static int cci_probe(struct platform_device *pdev) return dev_err_probe(dev, -EINVAL, "not enough clocks in DT\n"); cci->nclocks = ret; + cci->cci_clk = devm_clk_get(dev, "cci"); + if (IS_ERR(cci->cci_clk)) + return dev_err_probe(dev, PTR_ERR(cci->cci_clk), + "failed to get CCI clock\n"); + + ret = devm_pm_opp_set_clkname(dev, "cci"); + if (ret) + return dev_err_probe(dev, ret, "failed to set CCI OPP clk\n"); + + /* OPP table is optional */ + ret = devm_pm_opp_of_add_table(dev); + if (ret && ret != -ENODEV) + return dev_err_probe(dev, ret, "failed to add OPP table\n"); + + ret = cci_set_core_rate(cci, cci->data->cci_clk_rate); + if (ret) + return dev_err_probe(dev, ret, "failed to set CCI clock rate\n"); + ret = cci_enable_clocks(cci); if (ret < 0) return ret; -- 2.34.1