From: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
Jagadeesh Kona <quic_jkona@quicinc.com>,
Taniya Das <taniya.das@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Subject: [PATCH 2/2] clk: qcom: Add support for camera clock controller on Maili
Date: Mon, 27 Jul 2026 23:59:10 +0530 [thread overview]
Message-ID: <20260727-maili_camcc-v1-2-01dbd7ddb276@oss.qualcomm.com> (raw)
In-Reply-To: <20260727-maili_camcc-v1-0-01dbd7ddb276@oss.qualcomm.com>
Maili camcc is mostly identical to Hawi camcc, with a few clocks
removed, frequency table updates for a few other clocks, and PLL
configuration changes. Hence, reuse the Hawi camera clock controller
driver and extend it for the Qualcomm Maili SoC.
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
---
drivers/clk/qcom/camcc-hawi.c | 158 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 158 insertions(+)
diff --git a/drivers/clk/qcom/camcc-hawi.c b/drivers/clk/qcom/camcc-hawi.c
index 5b004a627fddead1e7d229bcc8f7c2bfae3560a0..e56afb42edd397945a486181cf120f30aed39c3a 100644
--- a/drivers/clk/qcom/camcc-hawi.c
+++ b/drivers/clk/qcom/camcc-hawi.c
@@ -61,6 +61,18 @@ static const struct alpha_pll_config cam_cc_pll0_config = {
.user_ctl_hi_val = 0x00000002,
};
+/* 1200.0 MHz Configuration */
+static const struct alpha_pll_config cam_cc_pll0_config_maili = {
+ .l = 0x3e,
+ .cal_l = 0x42,
+ .alpha = 0x8000,
+ .config_ctl_val = 0xa5c400e7,
+ .config_ctl_hi_val = 0x0a806160,
+ .config_ctl_hi1_val = 0xf51dea20,
+ .user_ctl_val = 0x00008400,
+ .user_ctl_hi_val = 0x00000002,
+};
+
static struct clk_alpha_pll cam_cc_pll0 = {
.offset = 0x0,
.config = &cam_cc_pll0_config,
@@ -136,6 +148,18 @@ static const struct alpha_pll_config cam_cc_pll1_config = {
.user_ctl_hi_val = 0x00000002,
};
+/* 493.2 MHz Configuration */
+static const struct alpha_pll_config cam_cc_pll1_config_maili = {
+ .l = 0x19,
+ .cal_l = 0x42,
+ .alpha = 0xb000,
+ .config_ctl_val = 0xa5c400e7,
+ .config_ctl_hi_val = 0x0a806160,
+ .config_ctl_hi1_val = 0xf51dea20,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000002,
+};
+
static struct clk_alpha_pll cam_cc_pll1 = {
.offset = 0x1000,
.config = &cam_cc_pll1_config,
@@ -188,6 +212,18 @@ static const struct alpha_pll_config cam_cc_pll2_config = {
.user_ctl_hi_val = 0x00000002,
};
+/* 600.0 MHz Configuration */
+static const struct alpha_pll_config cam_cc_pll2_config_maili = {
+ .l = 0x1f,
+ .cal_l = 0x42,
+ .alpha = 0x4000,
+ .config_ctl_val = 0xa5c400e7,
+ .config_ctl_hi_val = 0x0a806160,
+ .config_ctl_hi1_val = 0xf51dea20,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000002,
+};
+
static struct clk_alpha_pll cam_cc_pll2 = {
.offset = 0x2000,
.config = &cam_cc_pll2_config,
@@ -240,6 +276,18 @@ static const struct alpha_pll_config cam_cc_pll3_config = {
.user_ctl_hi_val = 0x00000002,
};
+/* 476.4 MHz Configuration */
+static const struct alpha_pll_config cam_cc_pll3_config_maili = {
+ .l = 0x18,
+ .cal_l = 0x42,
+ .alpha = 0xd000,
+ .config_ctl_val = 0xa5c400e7,
+ .config_ctl_hi_val = 0x0a806160,
+ .config_ctl_hi1_val = 0xf51dea20,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000002,
+};
+
static struct clk_alpha_pll cam_cc_pll3 = {
.offset = 0x3000,
.config = &cam_cc_pll3_config,
@@ -292,6 +340,18 @@ static const struct alpha_pll_config cam_cc_pll4_config = {
.user_ctl_hi_val = 0x00000002,
};
+/* 476.4 MHz Configuration */
+static const struct alpha_pll_config cam_cc_pll4_config_maili = {
+ .l = 0x18,
+ .cal_l = 0x42,
+ .alpha = 0xd000,
+ .config_ctl_val = 0xa5c400e7,
+ .config_ctl_hi_val = 0x0a806160,
+ .config_ctl_hi1_val = 0xf51dea20,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000002,
+};
+
static struct clk_alpha_pll cam_cc_pll4 = {
.offset = 0x4000,
.config = &cam_cc_pll4_config,
@@ -344,6 +404,18 @@ static const struct alpha_pll_config cam_cc_pll5_config = {
.user_ctl_hi_val = 0x00000002,
};
+/* 476.4 MHz Configuration */
+static const struct alpha_pll_config cam_cc_pll5_config_maili = {
+ .l = 0x18,
+ .cal_l = 0x42,
+ .alpha = 0xd000,
+ .config_ctl_val = 0xa5c400e7,
+ .config_ctl_hi_val = 0x0a806160,
+ .config_ctl_hi1_val = 0xf51dea20,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000002,
+};
+
static struct clk_alpha_pll cam_cc_pll5 = {
.offset = 0x5000,
.config = &cam_cc_pll5_config,
@@ -396,6 +468,18 @@ static const struct alpha_pll_config cam_cc_pll6_config = {
.user_ctl_hi_val = 0x00000002,
};
+/* 960.0 MHz Configuration */
+static const struct alpha_pll_config cam_cc_pll6_config_maili = {
+ .l = 0x32,
+ .cal_l = 0x42,
+ .alpha = 0x0,
+ .config_ctl_val = 0xa5c400e7,
+ .config_ctl_hi_val = 0x0a806160,
+ .config_ctl_hi1_val = 0xf51dea20,
+ .user_ctl_val = 0x00008400,
+ .user_ctl_hi_val = 0x00000002,
+};
+
static struct clk_alpha_pll cam_cc_pll6 = {
.offset = 0x6000,
.config = &cam_cc_pll6_config,
@@ -471,6 +555,18 @@ static const struct alpha_pll_config cam_cc_pll7_config = {
.user_ctl_hi_val = 0x00000002,
};
+/* 345.0 MHz Configuration */
+static const struct alpha_pll_config cam_cc_pll7_config_maili = {
+ .l = 0x11,
+ .cal_l = 0x42,
+ .alpha = 0xf800,
+ .config_ctl_val = 0xa5c400e7,
+ .config_ctl_hi_val = 0x0a806160,
+ .config_ctl_hi1_val = 0xf51dea20,
+ .user_ctl_val = 0x00000000,
+ .user_ctl_hi_val = 0x00000002,
+};
+
static struct clk_alpha_pll cam_cc_pll7 = {
.offset = 0x7000,
.config = &cam_cc_pll7_config,
@@ -500,6 +596,18 @@ static const struct alpha_pll_config cam_cc_pll8_config = {
.user_ctl_hi_val = 0x00000002,
};
+/* 493.2 MHz Configuration */
+static const struct alpha_pll_config cam_cc_pll8_config_maili = {
+ .l = 0x19,
+ .cal_l = 0x42,
+ .alpha = 0xb000,
+ .config_ctl_val = 0xa5c400e7,
+ .config_ctl_hi_val = 0x0a806160,
+ .config_ctl_hi1_val = 0xf51dea20,
+ .user_ctl_val = 0x00000400,
+ .user_ctl_hi_val = 0x00000002,
+};
+
static struct clk_alpha_pll cam_cc_pll8 = {
.offset = 0x8000,
.config = &cam_cc_pll8_config,
@@ -677,6 +785,17 @@ static const struct freq_tbl ftbl_cam_cc_camnoc_rt_axi_clk_src[] = {
{ }
};
+static const struct freq_tbl ftbl_cam_cc_camnoc_rt_axi_clk_src_maili[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 6, 0, 0),
+ F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0),
+ F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
+ F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
+ F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
+ F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
static struct clk_rcg2 cam_cc_camnoc_rt_axi_clk_src = {
.cmd_rcgr = 0x212cc,
.mnd_width = 0,
@@ -698,6 +817,11 @@ static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
{ }
};
+static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src_maili[] = {
+ F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
+ { }
+};
+
static struct clk_rcg2 cam_cc_cci_0_clk_src = {
.cmd_rcgr = 0x21250,
.mnd_width = 8,
@@ -1071,6 +1195,17 @@ static const struct freq_tbl ftbl_cam_cc_ofe_clk_src[] = {
{ }
};
+static const struct freq_tbl ftbl_cam_cc_ofe_clk_src_maili[] = {
+ F(300000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
+ F(376000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
+ F(445000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
+ F(500000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
+ F(609000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
+ F(688000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
+ F(841000000, P_CAM_CC_PLL2_OUT_EVEN, 1, 0, 0),
+ { }
+};
+
static struct clk_rcg2 cam_cc_ofe_clk_src = {
.cmd_rcgr = 0x20120,
.mnd_width = 0,
@@ -2961,12 +3096,35 @@ static const struct qcom_cc_desc cam_cc_hawi_desc = {
static const struct of_device_id cam_cc_hawi_match_table[] = {
{ .compatible = "qcom,hawi-camcc" },
+ { .compatible = "qcom,maili-camcc" },
{ }
};
MODULE_DEVICE_TABLE(of, cam_cc_hawi_match_table);
static int cam_cc_hawi_probe(struct platform_device *pdev)
{
+ if (device_is_compatible(&pdev->dev, "qcom,maili-camcc")) {
+ cam_cc_pll0.config = &cam_cc_pll0_config_maili;
+ cam_cc_pll1.config = &cam_cc_pll1_config_maili;
+ cam_cc_pll2.config = &cam_cc_pll2_config_maili;
+ cam_cc_pll3.config = &cam_cc_pll3_config_maili;
+ cam_cc_pll4.config = &cam_cc_pll4_config_maili;
+ cam_cc_pll5.config = &cam_cc_pll5_config_maili;
+ cam_cc_pll6.config = &cam_cc_pll6_config_maili;
+ cam_cc_pll7.config = &cam_cc_pll7_config_maili;
+ cam_cc_pll8.config = &cam_cc_pll8_config_maili;
+
+ cam_cc_camnoc_rt_axi_clk_src.freq_tbl = ftbl_cam_cc_camnoc_rt_axi_clk_src_maili;
+ cam_cc_cci_0_clk_src.freq_tbl = ftbl_cam_cc_cci_0_clk_src_maili;
+ cam_cc_ofe_clk_src.freq_tbl = ftbl_cam_cc_ofe_clk_src_maili;
+
+ cam_cc_hawi_clocks[CAM_CC_CCI_2_CLK_SRC] = NULL;
+ cam_cc_hawi_clocks[CAM_CC_CCI_2_CLK] = NULL;
+ cam_cc_hawi_clocks[CAM_CC_CSI5PHYTIMER_CLK_SRC] = NULL;
+ cam_cc_hawi_clocks[CAM_CC_CSI5PHYTIMER_CLK] = NULL;
+ cam_cc_hawi_clocks[CAM_CC_CSIPHY5_CLK] = NULL;
+ }
+
return qcom_cc_probe(pdev, &cam_cc_hawi_desc);
}
--
2.34.1
next prev parent reply other threads:[~2026-07-27 18:29 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-27 18:29 [PATCH 0/2] clk: qcom: Add camera clock controllers support for Qualcomm Maili SoC Jagadeesh Kona
2026-07-27 18:29 ` [PATCH 1/2] dt-bindings: clock: qcom: Add Maili camera clock controllers Jagadeesh Kona
2026-07-27 18:29 ` Jagadeesh Kona [this message]
2026-07-28 6:46 ` [PATCH 2/2] clk: qcom: Add support for camera clock controller on Maili Taniya Das
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