From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C31F4582CD for ; Tue, 28 Jul 2026 15:01:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785250871; cv=none; b=jaykkPNDTTtOk/zaKOiNBbi708ztR5uiXZML5Cw5TNAUWs8ze82Lf224ksM1DMvKM/c5L12q4bJKR8lpkBGYFpwEwdZgsd0GFRd58XXXjrGsL7ZNBoxQTTEj2wmdId3K7qfdXvc1cXord0JUvLsDdkx9xzYB9NSDdGkjfdJ9g5w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785250871; c=relaxed/simple; bh=f6LWsdlQRNCDjNfmjqIgrjJaREjsTccjnyUpFnI3K7Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gW6yu3ttpdNkZlLUT/WVa1UkM4Lsgr4Q/TofcnuFdMX09SkjbrsMmR4h9gxkLSIxhAC6OgerYFiSM3haIRTo6GNApsDkaaJk6ZQoZI4kfUIpN+lC5lCnttdPG4mvmKyvWapZyo0iKgejV5AMgtVsLdR8Wf1/gmwTzE3DqokLRbA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ycYRs7Td; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ycYRs7Td" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-47f6609c657so1918914f8f.2 for ; Tue, 28 Jul 2026 08:01:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1785250867; x=1785855667; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=JOI4iqJGtfH03pNuTKdAQXn1ZscdYwSeAfZivBz9ZJY=; b=ycYRs7TdKf0hlQq9UG0vFuvnuXrQ5riYjIr+vVhR5CBcDMiraKj3WwbeI2LHJBb1cK jMj9TUkq3hwwVWEcTsW8mw4j3jthDLXG3OqC+OCj8oh/sfB2wdB5y9ukILirnIvx4hPc s7F0NBhoMwy4u+Ob4aGpvbf1rgOi3BI+qggZAESAAotVYtw1ZIUKmRLcHOT2eLFOuaA6 +Qi5RAPngcvB+J71+DkWLe417PtVTUXKco/jAJC+QQ5nWScSGisE0N8Un1JROheJ6K5d eZkv8axOkr4eHdBXk/uxKzrBFq9rIvXrbNaxkx9b2eMhN/D7/sVFGdfAKELDqsABT8C3 W+dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785250867; x=1785855667; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=JOI4iqJGtfH03pNuTKdAQXn1ZscdYwSeAfZivBz9ZJY=; b=NO2UQ8OuJrarc2BJKh/8BamHOOQP/+3Hip9Tnd5jDJKCDvOMebpoJ9YdO+uY6KMDOC FdJORh9PyGOWCVSOzpSuCcP98Ny7bnsSn1sEXElwXiovFu9K6LMwJehgs84VThiXTs1Y i4LVuxo+FDxLcu1wVxr1qwgVw6/AkKPa6u81qKIGA//otQBvt7l0qYS01L3oh9Tmp+Sp CPOl+6lsu7UuQN9IvkbAc1hQbels7VddJVJExxUWNxaHO8G0qkzhK2vaTjWnzAPSfPw+ Q28zAlZHvpFNYkc9G/DrTmL+F4LoaFj7h4AKfe4SNs01ioo0PzPFHcX09EHiyvYWrgUr rbBw== X-Forwarded-Encrypted: i=1; AHgh+Ro/+elxb7dhch/+kQOicBAs0OmtFS6ZXwA1NdXVijNa+MpRWqODgMJqV8nO0bL3171jphjwx/Reh56ZMJg=@vger.kernel.org X-Gm-Message-State: AOJu0Yysq4wrZOMJyhnvLu/SEjXjjqPQ8V/VrQX8RnX0MAjqnvyLycta M8JBSF5QntXKdU5UaoRbY3qE2JiuyhBY/ptiV73zcuUmrpHX9WOfoUJ9aHLYgX5mn0c= X-Gm-Gg: AR+sD12fS9KLwluIIOl7T0qOc7Y+k05Yxnf2PnQT5iQKefh2o+szFoW/2s/9ivCvZPe odrAr9szmDiSnNH2Re18JMDTBFzDK0+AlhxWalyHTAqK5CwI9ZU4hjqN0OPWSecwmHamaJBrteL WGuQCTzJMTH8c5J7RdBxnNQRa1n6RvjQJxCG/d1n9JD+kks6oISSfEjqk0XcfPvHJuioOylXLfH QEY6qbRy6K6pPUTPnMitXmqqFzTtfWfjSdyl9f6t1t/q8x6GdbzLhYX39+oi918/klP5PNJQfMv yEvpFegfbdEoMH0aGdJoZaoaCsZb8oY0/iLXJ5I6WUzqoVyOKmI2Q74NEfjn/JrCUMr8Zdv/MuV YoF/5JlFtOE5nl4ILpd4teDr74Yw0MJ3AHP2QH01459BredLBcH66MeX/0NJNaJef0i30PNqByp 144uUyAiUjz4R7y+UhNA== X-Received: by 2002:a05:6000:4918:b0:47f:86af:8fdd with SMTP id ffacd0b85a97d-47fb1e5cde7mr3215692f8f.3.1785250867183; Tue, 28 Jul 2026 08:01:07 -0700 (PDT) Received: from [192.168.1.3] ([37.18.141.193]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f85c52fa9sm61036324f8f.20.2026.07.28.08.01.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2026 08:01:06 -0700 (PDT) From: James Clark Date: Tue, 28 Jul 2026 16:00:18 +0100 Subject: [PATCH v3 6/8] coresight: tmc-etf: Prevent per-thread events from sharing a sink Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260728-james-cs-multiple-per-threads-v3-6-6aee7579f1dc@linaro.org> References: <20260728-james-cs-multiple-per-threads-v3-0-6aee7579f1dc@linaro.org> In-Reply-To: <20260728-james-cs-multiple-per-threads-v3-0-6aee7579f1dc@linaro.org> To: Suzuki K Poulose , Mike Leach , Leo Yan , Suyash Mahar , Yeoreum Yun Cc: Greg Kroah-Hartman , Qi Liu , Junhao He , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, James Clark , Jonathan Cameron X-Mailer: b4 0.14.0 Like the previous commit to ETR, ETF sinks shouldn't share per-thread events. Fix it by returning -EBUSY if a second per-thread event tries to use the same sink. Fixes: 880af782c6e8 ("coresight: tmc-etf: Add support for CPU-wide trace scenarios") Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-tmc-core.c | 2 -- drivers/hwtracing/coresight/coresight-tmc-etf.c | 23 +++++++---------------- drivers/hwtracing/coresight/coresight-tmc.h | 4 ---- 3 files changed, 7 insertions(+), 22 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 873868718b14..2c2f2f312e8e 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -800,8 +800,6 @@ static int __tmc_probe(struct device *dev, struct resource *res) devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID); drvdata->config_type = BMVAL(devid, 6, 7); drvdata->memwidth = tmc_get_memwidth(devid); - /* This device is not associated with a session */ - drvdata->pid = -1; drvdata->etr_mode = ETR_MODE_AUTO; if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) { diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index d90090b846ab..c451f1da3cdd 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -250,11 +250,10 @@ static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, struct coresight_path *path) { int ret = 0; - pid_t pid; unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); struct perf_output_handle *handle = path->handle; - struct cs_buffers *buf = etm_perf_sink_config(handle); + struct etm_event_data *event_data = perf_get_aux(handle); raw_spin_lock_irqsave(&drvdata->spinlock, flags); do { @@ -270,10 +269,8 @@ static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, break; } - /* Get a handle on the pid of the process to monitor */ - pid = buf->pid; - - if (drvdata->pid != -1 && drvdata->pid != pid) { + if (!etm_perf_sink_can_share(csdev, &drvdata->perf_session, + handle)) { ret = -EBUSY; break; } @@ -282,19 +279,15 @@ static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, if (ret) break; - /* - * No HW configuration is needed if the sink is already in - * use for this session. - */ - if (drvdata->pid == pid) { + /* No HW configuration is needed if the sink is already in use. */ + if (csdev->refcnt) { csdev->refcnt++; break; } ret = tmc_etb_enable_hw(drvdata); if (!ret) { - /* Associate with monitored process. */ - drvdata->pid = pid; + drvdata->perf_session = event_data->session_id; coresight_set_mode(csdev, CS_MODE_PERF); csdev->refcnt++; } @@ -351,9 +344,8 @@ static int tmc_disable_etf_sink(struct coresight_device *csdev) /* Complain if we (somehow) got out of sync */ WARN_ON_ONCE(coresight_get_mode(csdev) == CS_MODE_DISABLED); tmc_etb_disable_hw(drvdata); - /* Dissociate from monitored process. */ - drvdata->pid = -1; coresight_set_mode(csdev, CS_MODE_DISABLED); + drvdata->perf_session = (struct etm_session_id) {}; raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -433,7 +425,6 @@ static void *tmc_alloc_etf_buffer(struct coresight_device *csdev, if (!buf) return NULL; - buf->pid = task_pid_nr(event->owner); buf->snapshot = overwrite; buf->nr_pages = nr_pages; buf->data_pages = pages; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 0125f2ad78ed..99601ac9179d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -223,9 +223,6 @@ struct tmc_resrv_buf { * @crashdev: specifics to handle "/dev/crash_tmc_xyz" entry for reading * crash tracedata. * @spinlock: only one at a time pls. - * @pid: Process ID of the process that owns the session that is using - * this component. For example this would be the pid of the Perf - * process. * @sysfs_reading: Sysfs mode buffer is being read through "/dev/xyz.tmc" entry. * Note: ETR has a separate software buffer for the two modes so * the device can still be read while in Perf mode if there is a @@ -264,7 +261,6 @@ struct tmc_drvdata { struct miscdevice miscdev; struct miscdevice crashdev; raw_spinlock_t spinlock; - pid_t pid; bool sysfs_reading; bool stop_on_flush; union { -- 2.34.1