From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C9775437111 for ; Tue, 28 Jul 2026 12:39:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785242393; cv=none; b=rk3p1asEsAgnqb7+3oZzV60WsNCC6tuIhCXVnJ8aCEaPHWWO9v6Ag5zp3i6YqLdl2W4fQ9YposhEwcs19363/4bAa6yhR3Kjc4Fl3WEcFeHyz3JP+YthTOhplXDbdO+SXrFOY8LhTfPuU1APEJmv73K2XVvYGL0BuH+eFXoXRe8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785242393; c=relaxed/simple; bh=ubd5mRvutCqeEAsJd3TBfy4XL/5Y9V9cf3fTX26dUV0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=X8bxCd6xfbVYmtLW+p61QmSmk3W8dRd//17/7pSLJEBDf9G4xeqVquIKKk6LQtmAOrTVvs8DZt5JeiPX56bpEDdfgktgwuRCa4r2Tnp77jAv3ejDWtbynP/sGH3Ff2Lw5q48KF1j93VrYy8p6ptUzCDUDHZjEvY/WHmljrurcY0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=YP9rdioV; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="YP9rdioV" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2CF0D1BC0; Tue, 28 Jul 2026 05:39:47 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 68E6B3F86F; Tue, 28 Jul 2026 05:39:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1785242391; bh=ubd5mRvutCqeEAsJd3TBfy4XL/5Y9V9cf3fTX26dUV0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YP9rdioV64XM9RT+7xZkNJyJ7bE94tsAlSFSWfqBECchtvLIrt6UudbI91YszFZgX PwPRYs+IRFOgrYQSo06wAjraEwIriz071Uy6BsTdoH5ol+qRw0syhZs/oezWTNB1WG Gn6KKoN/N2Je0K8tUDttquQhrkNlyuQ4rM6Yk/b0= From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: ada.coupriediaz@arm.com, ardb@kernel.org, catalin.marinas@arm.com, hca@linux.ibm.com, linux-kernel@vger.kernel.org, mark.rutland@arm.com, maz@kernel.org, peterz@infradead.org, ruanjinjie@huawei.com, vladimir.murzin@arm.com, will@kernel.org, yang@os.amperecomputing.com Subject: [RFC PATCH 04/13] arm64: percpu: Factor out percpu offset asm Date: Tue, 28 Jul 2026 13:38:50 +0100 Message-Id: <20260728123859.2911495-5-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20260728123859.2911495-1-mark.rutland@arm.com> References: <20260728123859.2911495-1-mark.rutland@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Depending on whether the kernel runs at EL1 or EL2, the percpu offset is stored in either TPIDR_EL1 or TPIDR_EL2, and __kern_my_cpu_offset() uses an ALTERNATIVE() sequence to read the relevant TPIDR_ELx. In subsequent patches we'll need to read the percpu offset in other assembly sequences. Factor the ALTERNATIVE sequence out of __kern_my_cpu_offset() into a new __KERN_ASM_CPU_OFFSET() macro so that we can share the code sequence. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland Cc: Ada Couprie Diaz Cc: Ard Biesheuvel Cc: Catalin Marinas Cc: Jinjie Ruan Cc: Marc Zyngier Cc: Peter Zijlstra Cc: Vladimir Murzin Cc: Will Deacon Cc: Yang Shi --- arch/arm64/include/asm/percpu.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h index b57b2bb009677..98823c97d534c 100644 --- a/arch/arm64/include/asm/percpu.h +++ b/arch/arm64/include/asm/percpu.h @@ -29,6 +29,11 @@ static inline unsigned long __hyp_my_cpu_offset(void) return read_sysreg(tpidr_el2); } +#define __KERN_ASM_CPU_OFFSET(dst) \ + ALTERNATIVE("mrs " dst ", tpidr_el1", \ + "mrs " dst ", tpidr_el2", \ + ARM64_HAS_VIRT_HOST_EXTN) + static inline unsigned long __kern_my_cpu_offset(void) { unsigned long off; @@ -37,11 +42,11 @@ static inline unsigned long __kern_my_cpu_offset(void) * We want to allow caching the value, so avoid using volatile and * instead use a fake stack read to hazard against barrier(). */ - asm(ALTERNATIVE("mrs %0, tpidr_el1", - "mrs %0, tpidr_el2", - ARM64_HAS_VIRT_HOST_EXTN) - : "=r" (off) : - "Q" (*(const unsigned long *)current_stack_pointer)); + asm( + __KERN_ASM_CPU_OFFSET("%0") + : "=r" (off) + : "Q" (*(const unsigned long *)current_stack_pointer) + ); return off; } -- 2.30.2