From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A1307438FF3 for ; Tue, 28 Jul 2026 12:39:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785242396; cv=none; b=juX/aj0Uap7THK+lrf4/92mU5TvDGpo1q93SjtpYdTwkwh45BkqNp7Z++JoOPJciFy0cX1KSC15qMu2cZW7MGGtFjhHKQ+7FRKlUn9J70W4QhPqCqTRWGBMpA/ntL3CcnRnzL9RucFLk0SISU3qHHp/+QuLVlireCZRYV5OHjvU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785242396; c=relaxed/simple; bh=uoFKcLbZS4KHZXEKTdLsc0hmo8Yp+pZmDr8NaV3E3oA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=j6QwubGGocd6V83ANmfIoOE+hxF6ZBkTJoCz48ek4gFTCXBF6r/zaGOwE5kYdi21YP0vRQ8iBwO/mORB5zjXbqjaPF2I3XRSqRE6cP1E/gBgnZtfFqWlKgrAmQTt+WWRjgHnB5VxUUFa9WLxHto1Jf61iY/qoxRsYAYFujzlltU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=E3u8BIcP; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="E3u8BIcP" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F0F0C175D; Tue, 28 Jul 2026 05:39:49 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 396E93F86F; Tue, 28 Jul 2026 05:39:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1785242394; bh=uoFKcLbZS4KHZXEKTdLsc0hmo8Yp+pZmDr8NaV3E3oA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=E3u8BIcPvUfELlx3Jlj8HFnVZDFQ9+5quDkR/d3NUExpVISKG+Tbf2MMJ59eIa51Z D2BqlBHkDzgX72qE83cpP/LfPYnYsdDr0sFSuhKe5nnsN14yuI+RvaaDBMjhWKTXIn NzB8htZSvLnM0wfjv/iKpK32m4gV4ZDYnH3VQyPw= From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: ada.coupriediaz@arm.com, ardb@kernel.org, catalin.marinas@arm.com, hca@linux.ibm.com, linux-kernel@vger.kernel.org, mark.rutland@arm.com, maz@kernel.org, peterz@infradead.org, ruanjinjie@huawei.com, vladimir.murzin@arm.com, will@kernel.org, yang@os.amperecomputing.com Subject: [RFC PATCH 05/13] arm64: gpr-num: Add wxN aliases for wN registers Date: Tue, 28 Jul 2026 13:38:51 +0100 Message-Id: <20260728123859.2911495-6-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20260728123859.2911495-1-mark.rutland@arm.com> References: <20260728123859.2911495-1-mark.rutland@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Some A64 instructions require a W register name for specific register arguments, and will not accept an X register name. For example: STRH , [, (|){, {}}] This is painful when writing macros for inline assembly, especially where a single register is used as both an X register and a W register. We solve this for plain assembly by adding a wxN alias for each xN register in commit: 4c4dcd3541f83d21 ("arm64: assembler: introduce wxN aliases for wN registers") Add the same facility for inline assembly, with a new __DEFINE_ASM_GPR_ALIASES macro. As with the other macros in gpr-num.h, different escaping is necessary for inline vs non-inline assembly, so we can't share a single definition that we stringify(). Signed-off-by: Mark Rutland Cc: Ada Couprie Diaz Cc: Ard Biesheuvel Cc: Catalin Marinas Cc: Jinjie Ruan Cc: Marc Zyngier Cc: Peter Zijlstra Cc: Vladimir Murzin Cc: Will Deacon Cc: Yang Shi --- arch/arm64/include/asm/gpr-num.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/include/asm/gpr-num.h b/arch/arm64/include/asm/gpr-num.h index a114e4f8209b0..240cd25d55c5a 100644 --- a/arch/arm64/include/asm/gpr-num.h +++ b/arch/arm64/include/asm/gpr-num.h @@ -21,6 +21,11 @@ " .equ .L__gpr_num_xzr, 31\n" \ " .equ .L__gpr_num_wzr, 31\n" +#define __DEFINE_ASM_GPR_ALIASES \ +" .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \ +" wx\\n .req w\\n\n" \ +" .endr\n" + #endif /* __ASSEMBLER__ */ #endif /* __ASM_GPR_NUM_H */ -- 2.30.2