From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from casper.infradead.org (casper.infradead.org [90.155.50.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0768D38E8AC for ; Tue, 28 Jul 2026 16:46:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=90.155.50.34 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785257201; cv=none; b=ftFh+NFFQUrcoY/9gZ4aC7vuEbaP8mq+Uso3vjHn9ZsLdxcQLDA+tymu1hf6pXVnrrjj8L0KJQMxqQLj9lzezPpgE2CXjzptdzxhQfW6Zi/EnxInbaxUGXdZ/e16BVKaHEwNNM+mea/U8sVRjOT02HrGC6XpUMgQBMMp8wnCmzw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785257201; c=relaxed/simple; bh=qIT+5PaccbQgnxgPhRPVUwmhch0vEPZQPn/AJ1FrNYI=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=DuMw721WZQnNhLJUrVmAsffYdJSaNG4j8IHKk0fGifx1RJPAsNhWT1Qgl7rmB4SbnapRDuTW328cfNsDPjceVMniRVFZQHg9m8nDwnQNWZUzc51njDOwkENjXyb4KB4BTkp19O+LiEamxoTF1TKsro0NonoDeCqHbT3TLxUUNx0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org; spf=pass smtp.mailfrom=infradead.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b=t+Fzad79; arc=none smtp.client-ip=90.155.50.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=infradead.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="t+Fzad79" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=WOJiIG7Fzg5mQgt2+0WpqlAAuSEAOA6dEC8aqhbkyUU=; b=t+Fzad79Zr3+vQ5enAj2UuD4Z2 MSNUb4jwdnqiovZoMCG1mSIL7wkV8hm5ZyGS/9d3SpzFNitK866IYTAUHbTKp3iL9zOfGSSboz1gA bH/XINUktpJVpzIgzMywAS/abnygxGhCj3OhA1T4masB0gPArxqsp4++flvFS0NeamguQ6olDDGTM CQYKUg3Xv5mBogLXZ2Ue+i6snZx+xh0J1ywv5xeQmXP0d+np3qKdhrIhT9D53CEWIxKMv/euXnDlo es6wwn10Usq7YRl+bSxYnvbaI7dFHiirWO7ndYWEfYUXAHRTmQwmlRLnTcU74gWQ2b0Nj7dYNpnh/ EQCuwVkA==; Received: from 77-249-17-252.cable.dynamic.v4.ziggo.nl ([77.249.17.252] helo=noisy.programming.kicks-ass.net) by casper.infradead.org with esmtpsa (Exim 4.99.1 #2 (Red Hat Linux)) id 1wokwq-0000000Dk2O-2xUK; Tue, 28 Jul 2026 16:46:32 +0000 Received: by noisy.programming.kicks-ass.net (Postfix, from userid 1000) id C7FF1300969; Tue, 28 Jul 2026 18:46:31 +0200 (CEST) Date: Tue, 28 Jul 2026 18:46:31 +0200 From: Peter Zijlstra To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, ada.coupriediaz@arm.com, ardb@kernel.org, catalin.marinas@arm.com, hca@linux.ibm.com, linux-kernel@vger.kernel.org, maz@kernel.org, ruanjinjie@huawei.com, vladimir.murzin@arm.com, will@kernel.org, yang@os.amperecomputing.com Subject: Re: [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops Message-ID: <20260728164631.GJ651302@noisy.programming.kicks-ass.net> References: <20260728123859.2911495-1-mark.rutland@arm.com> <20260728123859.2911495-7-mark.rutland@arm.com> <20260728141958.GV751831@noisy.programming.kicks-ass.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Jul 28, 2026 at 04:53:52PM +0100, Mark Rutland wrote: > I was being lazy here relative to what we do for asm-extable.h. How > about I match the pattern there, and have: > > | #define PCPU_GPR_PCP_SHIFT 0 > | #define PCPU_GPR_PCP GENMASK(4, 0) > | #define PCPU_GPR_OFF_SHIFT 5 > | #define PCPU_GPR_OFF GENMASK(9, 5) > | #define PCPU_GPR_ADDR_SHIFT 10 > | #define PCPU_GPR_ADDR GENMASK(14, 10) > | > | #define __VAL_PCPU_GPRS(pcp, off, addr) \ > | "(" \ > | "(.L__gpr_num_" pcp " << " __stringify(PCPU_GPR_PCP_SHIFT) ") | " \ > | "(.L__gpr_num_" off " << " __stringify(PCPU_GPR_OFF_SHIFT) ") | " \ > | "(.L__gpr_num_" addr " << " __stringify(PCPU_GPR_ADDR_SHIFT) ")" \ > | ")" > > ... if that's any better? #define PCPU_GPR_BITS 5 #define __PCPU_GPR_MASK(_shift) GENMASK((_shift+PCPU_GPR_BITS-1), _shift) #define PCPU_GPR_PCP_SHIFT (0*PCPU_GPR_BITS) #define PCPU_GPR_OFF_SHIFT (1*PCPU_GPR_BITS) #define PCPU_GPR_ADDR_SHIFT (2*PCPU_GPR_BITS) #define PCPU_GPR_PCP __PCPU_GPR_MASK(PCPU_GPR_PCP_SHIFT) #define PCPU_GPR_OFF __PCPU_GPR_MASK(PCPU_GPR_OFF_SHIFT) #define PCPU_GPR_ADDR __PCPU_GPR_MASK(PCPU_GPR_ADDR_SHIFT) ?