From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E59337E5E8 for ; Tue, 28 Jul 2026 16:49:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=90.155.92.199 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785257398; cv=none; b=XikJwhXtZuIFOysL9dH5Aq8ZL7BkqlOU14fYAQjTy4qVJzzOyj12ggIPANAzd5YxhzeN/jmuUqb0mSywNx1U+VH0bFLTntd4J2HYtAkjRFHjofRQFnCLqW/b5/cpp9Xkv9SNcKroMLSYKcKqbwru4fyX9IeRHmgqlVS7cABLgHo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785257398; c=relaxed/simple; bh=MJDAEYvJ8+ZawXvSBL02jrmtexolC6FJ+/U2lKMuGrE=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=MfPj+izeBFrQ3XjChsH7fsgd8pa+eKD5zESAOWBdAQRRkiCQ0cny2jxI2CnbivKLDw4yg0K42jOv6K2uNQxcinAPAANCjmfVjAmW4EaCzm0rKvk51005UWTMJZArssiJ3mbwLRlJj9cqviYaxV9N2Ng8Crz/o3+nsGjuOhVDjLk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org; spf=pass smtp.mailfrom=infradead.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b=dv71xeQI; arc=none smtp.client-ip=90.155.92.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=infradead.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="dv71xeQI" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=eREpMj0ZZmpeGZqK2GLG6vzrtOqbxwprWLJjDDFIcSQ=; b=dv71xeQIT8W+FkLfel+kKQ8cPc 0+xy6sc0BZQWN4cv+DAI24coDA2xBZSN6D2EbRglDYlCcoN4Dgx+Dhma5+f8ksx1uEQyLcoA/EFH7 E448fKoaZbDJnQ+tG7bXSQIxh5sk1S0Ytv33fKsZHttWj3QQnJs4+o6EpmVfSLzfTEq0Wn87+DiGP +d++aedaRnxjfPHTpqAdJvLnUOTHEvLWNC8r11m80YqaNlNp6lMR7vCk2m3mARMIo84zmm+tDafyx u9em41/FxtXRgcfalQBUdlrqKJ2WAzvBRKvk1vqLCkCVe2LGbQc7cuyt6anGXgZKIkDMSBAu/Yi0i em4wpVxw==; Received: from 77-249-17-252.cable.dynamic.v4.ziggo.nl ([77.249.17.252] helo=noisy.programming.kicks-ass.net) by desiato.infradead.org with esmtpsa (Exim 4.99.2 #2 (Red Hat Linux)) id 1wol00-000000058Et-3Rgs; Tue, 28 Jul 2026 16:49:48 +0000 Received: by noisy.programming.kicks-ass.net (Postfix, from userid 1000) id 96EF13011E4; Tue, 28 Jul 2026 18:49:47 +0200 (CEST) Date: Tue, 28 Jul 2026 18:49:47 +0200 From: Peter Zijlstra To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, ada.coupriediaz@arm.com, ardb@kernel.org, catalin.marinas@arm.com, hca@linux.ibm.com, linux-kernel@vger.kernel.org, maz@kernel.org, ruanjinjie@huawei.com, vladimir.murzin@arm.com, will@kernel.org, yang@os.amperecomputing.com Subject: Re: [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops Message-ID: <20260728164947.GL651302@noisy.programming.kicks-ass.net> References: <20260728123859.2911495-1-mark.rutland@arm.com> <20260728123859.2911495-7-mark.rutland@arm.com> <20260728141958.GV751831@noisy.programming.kicks-ass.net> <20260728143016.GB921102@noisy.programming.kicks-ass.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Jul 28, 2026 at 05:03:57PM +0100, Mark Rutland wrote: > On Tue, Jul 28, 2026 at 04:30:16PM +0200, Peter Zijlstra wrote: > > On Tue, Jul 28, 2026 at 04:19:58PM +0200, Peter Zijlstra wrote: > > > On Tue, Jul 28, 2026 at 01:38:52PM +0100, Mark Rutland wrote: > > > > > > > With the scheme added in this patch, this can be compiled as: > > > > > > > > | : > > > > | mrs x2, sp_el0 > > > > | mov x4, #0xc80 > > > > | strh w4, [x2, #20] > > > > | mrs x4, tpidr_el1 > > > > | add x3, x0, x4 > > > > > > Which it then recomputes, and so is harmless. > > > > Here! > > > > > > | 1: ldxr x6, [x3] > > > > | add x6, x6, x1 > > > > | stxr w5, x6, [x3] > > > > | cbnz w5, 1b > > > > > > If we get here and interrupts happens, we recompute pointlessly, no harm > > > done. > > > > > > Anyway, per this sequence there is no point in ever doing the fixup. So > > > perhaps give a better example? > > > > Nevermind, brain just wasn't working right, when interrupt happens at > > 'Here!' above, it needs the fixup, irrespective of the atomic type. > > Yep! > > Note that the atomic type doesn't change things. We need the fixup even > if preemption happens *within* the LDXR...STXR loop, since the inline > sequences branches back to the LDXR, *without* recalculating the addr or > offset, and the fixup *does not* alter the PC. > > It's a bit awkaward to spell that out in the commit message without > unrolling the loop :/ Fair enough.