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charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDcyNL3Wxj3cTknMy8El1Lk+REyxTjNAtDizQloPqCotS0zAqwWdFKQW7 OSrEQweLSpKzU5BKQKUq1tQBGONS7cgAAAA== X-Change-ID: 20260729-k3-aclint-94ca9d3f818f To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Inochi Amaoto , Samuel Holland , Anup Patel , Guodong Xu Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Conor Dooley , Junhui Liu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4190; i=junhui.liu@pigmoral.tech; h=from:subject:message-id; bh=qU+HHx9IVqeto+Xj7vjzq5aDA4v1duGiO2ksgj3uRsc=; b=owGbwMvMwCWWvDb1VEXc8j+Mp9WSGLIybh31D5wn5tIlsTLoSUhcXNXWVU9Eohvur/1pNS/21 t4bM3iFOkpZGMS4GGTFFFm4/MX/WevwfDsi0HofZg4rE8gQBi5OAZiILRcjw7M/VZzdgRvbHWMs I+ouXuD0aNK+5Jy4sU76KX9EossZD4b/5YGbWOId09ra4x4zWIgvVtfuChLVK2fZ/GqlyKTbf7r 5AA== X-Developer-Key: i=junhui.liu@pigmoral.tech; a=openpgp; fpr=15B30CC69C4BF0CC3C08F85A2A90CDC122DF37BF X-ZohoMailClient: External When testing OpenSBI with the upstream Device Tree, the CLINT controller failed to function properly with the irqchip.riscv_imsic_noipi boot parameter: Platform IPI Device : aclint-mswi Platform Timer Device : aclint-mtimer @ 24000000Hz Domain0 Region03 : 0x00000000e081c000-0x00000000e081ffff M: (I,R,W) S/U: () [ 0.091014] smp: Bringing up secondary CPUs ... [ 10.104917] CPU1 failed to report alive state [ 20.118689] CPU2 failed to report alive state [ 30.132288] CPU3 failed to report alive state [ 40.145953] CPU4 failed to report alive state [ 50.159604] CPU5 failed to report alive state [ 60.173212] CPU6 failed to report alive state [ 70.186981] CPU7 failed to report alive state [ 70.191411] smp: Brought up 1 node, 1 CPU Through exploring and testing, I discovered that the K3 actually provides all three complete ACLINT components, and subsequent confirmation with the vendor yielded the following information: The ACLINT controllers are mapped to two physical memory regions: secure (0xf1810000-0xf1820000) and non-secure (0xe0810000-0xe0820000), with varying accessibility per controller and execution mode: +---------+--------+------------------------+-----------------------+ | Offset | Module | Secure Region | Non-Secure Region | +---------+--------+------------------------+-----------------------+ | +0x0000 | MSWI | 0xf1810000-0xf1813fff | 0xe0810000-0xe0813fff | | | | (M-mode only) | (Inaccessible) | +---------+--------+------------------------+-----------------------+ | +0x4000 | MTIMER | 0xf1814000-0xf181bfff | 0xe0814000-0xe081bfff | | | | (M-mode only) | (Inaccessible) | +---------+--------+------------------------+-----------------------+ | +0xc000 | SSWI | 0xf181c000-0xf181ffff | 0xe081c000-0xe081ffff | | | | (M-mode only if efused)| (M/S-mode Accessible) | +---------+--------+------------------------+-----------------------+ Taking these constraints into account, we choose the secure region (0xf1810000-0xf181bfff) for the M-mode ACLINT components (MSWI and MTIMER), and the non-secure region (0xe081c000-0xe081ffff) for the S-mode SSWI component. This series is marked as RFC to discuss the ACLINT compatible string strategy. Existing ACLINT compatibles in upstream carry specific quirks (e.g., Nuclei/T-Head MTIMER requiring 32-bit MMIO access, or MIPS SSWI adding extra DT properties). This series introduces the standard generic "riscv,aclint-*" fallback compatibles, similar to "riscv,imsics" and "riscv,aplic", to prevent constantly updating drivers for future SoCs. Feedback is welcomed on this approach versus potential alternatives, such as using standalone "spacemit,k3-aclint-*" compatibles without fallbacks, or selecting distinct existing fallbacks per ACLINT sub-module to bypass known vendor quirks. Signed-off-by: Junhui Liu --- Junhui Liu (7): dt-bindings: timer: thead,c900-aclint-mtimer: Add SpacemiT K3 dt-bindings: interrupt-controller: thead,c900-aclint-mswi: Add SpacemiT K3 dt-bindings: interrupt-controller: thead,c900-aclint-sswi: Add SpacemiT K3 dt-bindings: timer: sifive,clint: Mark spacemit,k3-clint as deprecated irqchip/aclint-sswi: Add generic riscv,aclint-sswi match riscv: dts: spacemit: k3: Fix SSWI node misidentified as CLINT riscv: dts: spacemit: k3: Add ACLINT MSWI and MTIMER nodes .../thead,c900-aclint-mswi.yaml | 4 +++ .../thead,c900-aclint-sswi.yaml | 4 +++ .../devicetree/bindings/timer/sifive,clint.yaml | 5 ++- .../bindings/timer/thead,c900-aclint-mtimer.yaml | 4 +++ arch/riscv/boot/dts/spacemit/k3.dtsi | 37 ++++++++++++++++------ drivers/irqchip/irq-aclint-sswi.c | 1 + 6 files changed, 44 insertions(+), 11 deletions(-) --- base-commit: 46380e4b1534c1626cecd7f4d0abb5e0cce09af6 change-id: 20260729-k3-aclint-94ca9d3f818f Best regards, -- Junhui Liu