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Wed, 29 Jul 2026 06:36:20 -0700 (PDT) Received: from chromium.org ([174.51.25.52]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-6aca527fe83sm1956196eaf.6.2026.07.29.06.36.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2026 06:36:19 -0700 (PDT) From: Simon Glass To: Heiko Stuebner Cc: Fabio Estevam , linux-rockchip@lists.infradead.org, Jonas Karlman , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Simon Glass , Albert Aribaud , Brian Masney , Chukun Pan , Conor Dooley , FUKAUMI Naoki , Jeffy Chen , Krzysztof Kozlowski , Michael Opdenacker , Michael Riesch , Michael Turquette , Rob Herring , Stephen Boyd , Vinod Koul , Yao Zi , huang lin , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 0/6] Add support for the Rockchip RV1106 and RV1103 Date: Wed, 29 Jul 2026 07:35:47 -0600 Message-ID: <20260729133609.3465563-1-sjg@chromium.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds initial support for the Rockchip RV1106, a Cortex-A7 SoC aimed at IP cameras, and its RV1103 package variant, together with the Luckfox Pico Mini B, a small and widely available RV1103 board. The series follows the structure of the recently merged RV1103B support. The clock driver is ported from the vendor kernel and is the work of Elaine Zhang. As with the RV1103B, no resets are exposed yet and the CPU pvtpll is initialised but not calibrated. Following feedback on v1, several parts have been split out into separate series: the pinctrl driver and binding, and the serial, watchdog and iio bindings, are submitted separately to their maintainers. The mmc binding is already applied for mmc-next. This series carries the clock support, the GRF compatibles and the devicetrees, which depend on the clock binding header. The devicetrees cover the devices needed for a basic system: UARTs, SD/eMMC, the SPI flash controller, SARADC, watchdog, GPIO and pinctrl. This v3 is re-tested on the Luckfox Pico Mini B: the kernel boots to the rootfs wait with a working console on UART2, timers, pinctrl and GPIO, and an SD card running at high speed. It builds with W=1 without warnings and dt_binding_check and dtbs_check are clean. Changes in v3: - Add IDs for the internal clocks, so that anonymous branches cannot overwrite the APLL entry in the clock array - Register the CRU as a platform driver, like the RK3528 - Give the internal clocks real IDs so that they cannot overwrite the APLL entry in the clock array - Drop the pre-mux write of the alternate divider, which overwrites the safe divider calculated by the CPU clock framework, and the post-mux write, which duplicates the framework's own clean-up - Add CLK_SET_RATE_PARENT to clk_vicap_m1_frac, matching m0 - Use a separate compatible for each GPIO IOC block, since their register layouts differ - Use the per-bank IOC compatibles - Place the entry with the other Luckfox boards, in alphabetical order Changes in v2: - Renumber the clock IDs to be continuous, starting from 0 - Provide the MMC phase clocks from the CRU rather than a grf-cru - Mention the MMC phase clocks in the rockchip,grf description - Provide the MMC phase clocks from the CRU via an auxiliary GRF regmap rather than from a separate grf-cru clock provider - Drop the grf-cru clock-controller child and use the syscon-only group for the main GRF, since the CRU now provides the MMC phase clocks - Use a single gpio-ioc compatible for the per-bank IOC blocks in place of the ioc and pmuioc regions - Take the MMC drive and sample phase clocks from the CRU and drop the grf-cru node - Give each GPIO bank a syscon for its own IOC block, referenced by a rockchip,grf phandle in the bank node - Add gpio aliases, which the pin controller and gpio drivers use to identify the bank; the rv1103 removes the gpio2 alias - Split the series by subsystem: pinctrl, serial, watchdog and iio are now submitted separately - Drop patch 'dt-bindings: mmc: rockchip-dw-mshc: Add RV1106 compatible', which is applied for mmc-next Simon Glass (6): dt-bindings: clock: rockchip: Add RV1106 CRU support clk: rockchip: Add clock controller for the RV1106 dt-bindings: soc: rockchip: grf: Add RV1106 compatibles ARM: dts: rockchip: Add support for RV1106 and RV1103 dt-bindings: arm: rockchip: Add Luckfox Pico Mini B ARM: dts: rockchip: Add Luckfox Pico Mini B .../devicetree/bindings/arm/rockchip.yaml | 5 + .../bindings/clock/rockchip,rv1106-cru.yaml | 60 + .../devicetree/bindings/soc/rockchip/grf.yaml | 6 + arch/arm/boot/dts/rockchip/Makefile | 1 + .../rockchip/rv1103-luckfox-pico-mini-b.dts | 93 ++ arch/arm/boot/dts/rockchip/rv1103.dtsi | 16 + .../arm/boot/dts/rockchip/rv1106-pinctrl.dtsi | 1398 +++++++++++++++++ arch/arm/boot/dts/rockchip/rv1106.dtsi | 321 ++++ drivers/clk/rockchip/Kconfig | 7 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-rv1106.c | 1099 +++++++++++++ .../dt-bindings/clock/rockchip,rv1106-cru.h | 306 ++++ 12 files changed, 3313 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml create mode 100644 arch/arm/boot/dts/rockchip/rv1103-luckfox-pico-mini-b.dts create mode 100644 arch/arm/boot/dts/rockchip/rv1103.dtsi create mode 100644 arch/arm/boot/dts/rockchip/rv1106-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/rockchip/rv1106.dtsi create mode 100644 drivers/clk/rockchip/clk-rv1106.c create mode 100644 include/dt-bindings/clock/rockchip,rv1106-cru.h --- base-commit: fc02acf6ac0ccde0c805c2daa9148683cdd01ba8 branch: rv1106a3 -- 2.43.0