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Wed, 29 Jul 2026 09:39:34 -0700 (PDT) From: Yu-Chien Peter Lin To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, samuel.holland@sifive.com, dlan@kernel.org, guodong@riscstar.com, dfustini@oss.tenstorrent.com, michal.simek@amd.com, junhui.liu@pigmoral.tech, darshan.prajapati@einfochips.com, akpm@linux-foundation.org, zhangchunyan@iscas.ac.cn, luxu.kernel@bytedance.com, pincheng.plct@isrc.iscas.ac.cn, nick.hu@sifive.com, jim.shu@sifive.com, zong.li@sifive.com, greentime.hu@sifive.com, robin.randhawa@sifive.com, scott@riscstar.com, dave.patel@riscstar.com, raymond.mao@riscstar.com, anup@brainfault.org, pawandeep.oza@oss.qualcomm.com, Yu-Chien Peter Lin Subject: [PATCH v2 1/3] dt-bindings: riscv: Add Worlds ISA extensions Date: Thu, 30 Jul 2026 00:39:06 +0800 Message-ID: <20260729163908.249838-2-peter.lin@sifive.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20260729163908.249838-1-peter.lin@sifive.com> References: <20260729163908.249838-1-peter.lin@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add DT bindings for five RISC-V Worlds ISA extensions that implement World ID tagging for hardware-enforced context isolation. Also, add checks for extension dependency requirements. Signed-off-by: Yu-Chien Peter Lin --- .../devicetree/bindings/riscv/extensions.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 2b0a8a93bb21..7a57191a0293 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -193,12 +193,35 @@ properties: ratified at commit d70011dde6c2 ("Update to ratified state") of riscv-j-extension. + - const: smlwid + description: | + The standard Smlwid extension for M-mode control of lower + privilege World ID via the mlwid CSR as ratified at commit + TBD ("TBD") of riscv-worlds. + + - const: smlwidlist + description: | + The standard Smlwidlist extension for M-mode control of lower + privilege World IDs via the mlwidlist CSR as ratified at commit + TBD ("TBD") of riscv-worlds. + - const: smstateen description: | The standard Smstateen extension for controlling access to CSRs added by other RISC-V extensions in H/S/VS/U/VU modes and as ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. + - const: smwiddeleg + description: | + The standard Smwiddeleg extension for M-mode delegation of lower + privilege World ID control to S-mode via the mwiddeleg CSR, as + ratified at commit TBD ("TBD") of riscv-worlds. + + - const: smwid + description: | + The standard Smwid extension for M-mode World ID control via the + mwid CSR as ratified at commit TBD ("TBD") of riscv-worlds. + - const: ssaia description: | The standard Ssaia supervisor-level extension for the advanced @@ -262,6 +285,12 @@ properties: ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated to ratified state.") + - const: sswid + description: | + The standard Sswid extension for S-mode control of lower + privilege World IDs via the slwid CSR as ratified at commit + TBD ("TBD") of riscv-worlds. + - const: supm description: | The standard Supm extension for pointer masking support in user @@ -924,6 +953,30 @@ properties: then: contains: const: b + # Smlwidlist depends on Smwid and Smlwid + - if: + contains: + const: smlwidlist + then: + allOf: + - contains: + const: smwid + - contains: + const: smlwid + # Smwiddeleg depends on Smlwid + - if: + contains: + const: smwiddeleg + then: + contains: + const: smlwid + # Sswid depends on Smwiddeleg + - if: + contains: + const: sswid + then: + contains: + const: smwiddeleg # Supm depends on Smnpm or Ssnpm - if: contains: -- 2.43.7