From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1AA33644A4 for ; Wed, 29 Jul 2026 17:28:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785346088; cv=none; b=BQIZ20i+7/8fcxFMMo3zmxitiRIZ2qWwCEOYotfWAMG9ry5UWcdvwEn+EetrJSNX2PIgFM2BG17kA1OomSwq17dMZKo9hAHgyRonoM5P24ykJIhH4UDkgzvhVAzbApyN+I7PvBFzNe1Wxwd/Wfxzxq8oezLoD1zNZF4Kqio9BJo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785346088; c=relaxed/simple; bh=56XBQvLIE964I8+e4wjw0yy5jJrbqZwWWyNQQL3+vg8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jH6t4d2z7c2SoLTa7MN0l5A7O+rkvlZgltSqdzNcIyWtTzsGdHnnUDVFe0tGjWqwlG1Xjx89UtgHsewrKOczYYpi+3t+gHRjKTMJHqZtUFu6i1ZBmyaR1pnXscsERvuI+MeEoPMHePXL49IkekHHlLpONUbsPEtM8EefnTpoG5A= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nTxQz85U; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nTxQz85U" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785346086; x=1816882086; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=56XBQvLIE964I8+e4wjw0yy5jJrbqZwWWyNQQL3+vg8=; b=nTxQz85U+PHRYKBrWlztQnAAteKvRfAk6FL/ChIK0JFRWuJOLtv9ivRV IVQKC032tolQMWujQ15NIb+XvNUeOZsDgupYus2PqRaE3fcVTlCFvApby PDGfZzP4zj8mqCEY0wmjKfywhXx3NCAg0I5+tPgmRHKHe3Ct0bY9OWlp+ St4hO0hngZ6PmxXD6W8GQqbDY4cn4W7UqTaDyhfIJK0V7lyHIueuaYJ7V xt0dh4gY4Lr5qBuXuTdNOxQKcJJklwHFZ2cMFRhPv+AALeDCVEhQzQPUw hFms0C80ADmwYHUfd9KpzyedE9x4+EinK0oFj9qRYCZGQsGslYtqmF518 w==; X-CSE-ConnectionGUID: tJeKR26uRE+1/5IOReJuaA== X-CSE-MsgGUID: U5tdxTTbQW2xxB0mSqOqQQ== X-IronPort-AV: E=McAfee;i="6800,10657,11859"; a="97473589" X-IronPort-AV: E=Sophos;i="6.25,192,1779174000"; d="scan'208";a="97473589" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2026 10:28:01 -0700 X-CSE-ConnectionGUID: aWwa7MgBRUG0fnLtCn/htg== X-CSE-MsgGUID: BjGVeylURwy7huCyKjN0BA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,192,1779174000"; d="scan'208";a="262024562" Received: from iherna2-mobl4.amr.corp.intel.com (HELO agluck-desk3.home.arpa) ([10.124.223.238]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jul 2026 10:28:01 -0700 From: Tony Luck To: Fenghua Yu , Reinette Chatre , Maciej Wieczor-Retman , Peter Newman , James Morse , Babu Moger , Drew Fustini , Dave Martin , Chen Yu , David E Box , x86@kernel.org Cc: Christoph Hellwig , linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v10 05/17] fs/resctrl: Add interface to disable a monitor event Date: Wed, 29 Jul 2026 10:27:40 -0700 Message-ID: <20260729172752.11561-6-tony.luck@intel.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260729172752.11561-1-tony.luck@intel.com> References: <20260729172752.11561-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit resctrl currently assumes all monitor events are enabled before any domain is created, because per-domain state is allocated by the architecture's CPU hotplug callbacks. There is no way to disable an event once registered. AET events are enumerated by the INTEL_PMT_TELEMETRY driver. To allow that driver to be a loadable module, resctrl must tolerate AET events appearing and disappearing, which requires the ability to disable an event when the driver is unloaded. Add resctrl_disable_mon_event(). The architecture owns domain lifetime and knows mount state, so it is responsible for calling this only while resctrl is unmounted and for cleaning up any per-domain state. Document those requirements in the kerneldoc since they are not enforced in code. Signed-off-by: Tony Luck --- v10: Unchanged since v9 include/linux/resctrl.h | 34 ++++++++++++++++++++++++++++++++++ fs/resctrl/monitor.c | 15 +++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index dd09c2ce9a0f..a184500745f8 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -419,9 +419,43 @@ u32 resctrl_arch_get_num_closid(struct rdt_resource *r); u32 resctrl_arch_system_num_rmid_idx(void); int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid); +/** + * resctrl_enable_mon_event() - Enable monitoring event + * @eventid: ID of the event + * @any_cpu: True if event data can be read from any CPU. + * @binary_bits: Number of binary places of the fixed-point value expected to + * back a floating point event. Can only be set for floating point + * events. + * @arch_priv: Architecture private data associated with event. Passed back to + * architecture when reading the event via resctrl_arch_rmid_read(). + * + * The file system must not be mounted when enabling an event. + * + * Events that require per-domain (architectural and/or filesystem) state must + * be enabled before the domain structures are allocated. For example before + * CPU hotplug callbacks that allocate domain structures are registered. If the + * architecture discovers a resource after initialization it should enable + * events needing per-domain state before any domain structure allocation which + * should be coordinated with the CPU hotplug callbacks. + * + * Return: + * true if event was successfully enabled, false otherwise. + */ bool resctrl_enable_mon_event(enum resctrl_event_id eventid, bool any_cpu, unsigned int binary_bits, void *arch_priv); +/** + * resctrl_disable_mon_event() - Disable monitoring event + * @eventid: ID of the event + * + * The file system must not be mounted when disabling an event. + * + * Events that require per-domain (architectural and/or filesystem) state + * will require additional cleanup which should be coordinated with the CPU + * hotplug callbacks. + */ +void resctrl_disable_mon_event(enum resctrl_event_id eventid); + bool resctrl_is_mon_event_enabled(enum resctrl_event_id eventid); bool resctrl_arch_is_evt_configurable(enum resctrl_event_id evt); diff --git a/fs/resctrl/monitor.c b/fs/resctrl/monitor.c index 6acf6106e6f1..d7ad976ed503 100644 --- a/fs/resctrl/monitor.c +++ b/fs/resctrl/monitor.c @@ -1066,6 +1066,21 @@ bool resctrl_enable_mon_event(enum resctrl_event_id eventid, bool any_cpu, return true; } +void resctrl_disable_mon_event(enum resctrl_event_id eventid) +{ + if (WARN_ON_ONCE(eventid < QOS_FIRST_EVENT || eventid >= QOS_NUM_EVENTS)) + return; + if (!mon_event_all[eventid].enabled) { + pr_warn("Event %d already disabled\n", eventid); + return; + } + + mon_event_all[eventid].any_cpu = false; + mon_event_all[eventid].binary_bits = 0; + mon_event_all[eventid].arch_priv = NULL; + mon_event_all[eventid].enabled = false; +} + bool resctrl_is_mon_event_enabled(enum resctrl_event_id eventid) { return eventid >= QOS_FIRST_EVENT && eventid < QOS_NUM_EVENTS && -- 2.55.0