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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d04b15d26esm719635ad.76.2026.07.30.23.14.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 23:14:52 -0700 (PDT) From: Gopikrishna Garmidi Date: Thu, 30 Jul 2026 23:14:38 -0700 Subject: [PATCH v4 2/5] arm64: dts: qcom: Add Kalambo SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260730-b4-kalambo-crd-v4-2-e458f8b08114@oss.qualcomm.com> References: <20260730-b4-kalambo-crd-v4-0-e458f8b08114@oss.qualcomm.com> In-Reply-To: <20260730-b4-kalambo-crd-v4-0-e458f8b08114@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Pankaj Patil Cc: Rajendra Nayak , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Gopikrishna Garmidi X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785478489; l=4284; i=gopikrishna.garmidi@oss.qualcomm.com; s=20260102; h=from:subject:message-id; bh=NkU3dFvQLNuVr0IO6l1ErGb6cSn9Tsn8pb/Xe/a6SHA=; b=wbmwo6Ii8Ofp0ydWufnhJs3SKIzU+S++IHsHEaUEQ8/xn8D8XhPGw46eKH+6g7c3nS/uqL4Y5 ZSNFGg/hBvKBHt2f19AXB2/d0GZt7J6hct4StYCuKYYlByssi7NYOU7 X-Developer-Key: i=gopikrishna.garmidi@oss.qualcomm.com; a=ed25519; pk=TkSjNEhrfsj90i3wkABTZtAjLNr2cfYsujaTvyOIDsE= X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMxMDA0MSBTYWx0ZWRfX/S7fxfeBIOPV jcxSYCp7IUklB5hlhICTwU5SJbmsQbcyyE8vHCvyy+iwqzP+rIqkIIj7oanHzBt9potnRFj36W3 NTAdHyHz4JS/dThSNsKCIvZUaVnWBJI= X-Authority-Analysis: v=2.4 cv=HJTz0Itv c=1 sm=1 tr=0 ts=6a6c3d5e cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=0meGOa8vbbZiQTQppSIA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: _MFZ2qzG_Cp3rahK82RuR1aOFfSy2f8U X-Proofpoint-GUID: _MFZ2qzG_Cp3rahK82RuR1aOFfSy2f8U X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMxMDA0MSBTYWx0ZWRfXygH6KSLOFWLB SO05l80eAgDGXFreHLugLWiNIr+wHFVq2/izY9VbDarw7io9SrTnV0VlCp4X8rBOmYOaPh8NpST JXjbLl8Cfd/BBSCwVb64GkucULrrD5JjOlhvNBxOkaOGZwsmdVE+28U5MzJXOZyJGwSZdQhyKxs 2V2qqhhF6jEqCcUyNcD1OZhiBjrWN1WLJJvKDbNs5iBgEpJGBGday1mFEJAbMAgZ/WrOLAHa4Y/ rZccA/eVjzXX8SdoVKCw/GH54tnM3912psB0yMXtywfMlhP9bKnSCVEgraqYsNpyXlKvEzDt6TE l41AuBGfnEpBf6zCBpdhkcn11nAYjwmlNNP5l7RLvnq+2FOtQ+UwUyqEBEIsFGqMKPvamdA4ec8 LKfVPesM6WyZsUSwVUXGCCiV+lfUhmSjccPF8qbBHZEO0cOo9OmJLwWPCBWWgHu0l3KvEFpIKxR 8guH0BNb4kbOfjRCXWA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-31_02,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 impostorscore=0 adultscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607310041 Introduce support for the Qualcomm Kalambo SoC. It is derived from Mahua with CPU cluster 0 removed, leaving it with just cluster 1 (cpu6-cpu11). The surviving cluster is re-added to the cpu-map as cluster0, since the kernel stops scanning at the first missing clusterN index. cpu6-cpu11 are reassigned to SCMI performance domain 0, as domain 1 is no longer present. Kalambo uses PDP1 whose tx shmem (lpri1) sits at offset 0x200 within imem, vs 0x180 on Glymur (PDP0). This pushes the tx region end to 0x380, requiring an imem size override. The rx shmem (lpri0) stays at offset 0x0. The PDP mailbox addresses are overridden to match the Kalambo SCP firmware. PDC pins 109 and 110 carry the tsens6 and tsens7 upper/lower interrupts, which are unconnected on Kalambo since both sensors are absent. Split the range starting at pin 108 to skip them. Add labels to the cpus and cpu-map nodes in Glymur to allow derived SoCs to delete and redefine the cpu-map entirely. Reviewed-by: Abel Vesa Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Signed-off-by: Gopikrishna Garmidi --- arch/arm64/boot/dts/qcom/glymur.dtsi | 4 +- arch/arm64/boot/dts/qcom/kalambo.dtsi | 112 ++++++++++++++++++++++++++++++++++ 2 files changed, 114 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 4be7edf894b5..3f1fd0973717 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -36,7 +36,7 @@ / { #address-cells = <2>; #size-cells = <2>; - cpus { + cpus: cpus { #address-cells = <2>; #size-cells = <0>; @@ -274,7 +274,7 @@ cpu17: cpu@20500 { #cooling-cells = <2>; }; - cpu-map { + cpu_map: cpu-map { cluster0 { core0 { cpu = <&cpu0>; diff --git a/arch/arm64/boot/dts/qcom/kalambo.dtsi b/arch/arm64/boot/dts/qcom/kalambo.dtsi new file mode 100644 index 000000000000..fb5d68bd69d7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kalambo.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "mahua.dtsi" + +/delete-node/ &cluster0_pd; +/delete-node/ &cpu_map; +/delete-node/ &cpu0; +/delete-node/ &cpu1; +/delete-node/ &cpu2; +/delete-node/ &cpu3; +/delete-node/ &cpu4; +/delete-node/ &cpu5; +/delete-node/ &cpu_pd0; +/delete-node/ &cpu_pd1; +/delete-node/ &cpu_pd2; +/delete-node/ &cpu_pd3; +/delete-node/ &cpu_pd4; +/delete-node/ &cpu_pd5; +/delete-node/ &cpu_scp_lpri1; + +&cpu6 { + power-domains = <&cpu_pd6>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; +}; + +&cpu7 { + power-domains = <&cpu_pd7>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; +}; + +&cpu8 { + power-domains = <&cpu_pd8>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; +}; + +&cpu9 { + power-domains = <&cpu_pd9>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; +}; + +&cpu10 { + power-domains = <&cpu_pd10>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; +}; + +&cpu11 { + power-domains = <&cpu_pd11>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; +}; + +&cpus { + cpu-map { + cluster0 { + core0 { + cpu = <&cpu6>; + }; + + core1 { + cpu = <&cpu7>; + }; + + core2 { + cpu = <&cpu8>; + }; + + core3 { + cpu = <&cpu9>; + }; + + core4 { + cpu = <&cpu10>; + }; + + core5 { + cpu = <&cpu11>; + }; + }; + }; +}; + +&imem { + reg = <0x0 0x81e08600 0x0 0x380>; + ranges = <0x0 0x0 0x81e08600 0x380>; + + cpu_scp_lpri1: scp-sram-section@200 { + compatible = "arm,scmi-shmem"; + reg = <0x200 0x180>; + }; +}; + +&pdc { + qcom,pdc-ranges = <0 745 38>, + <40 785 11>, + <51 527 4>, + <57 533 10>, + <70 546 4>, + <75 551 18>, + <108 619 1>, + <111 622 19>, + <130 717 12>, + <142 251 5>, + <147 796 16>, + <171 4104 36>; +}; + +&pdp0_mbox { + reg = <0x0 0x17610000 0x0 0x8000>, + <0x0 0x1a980000 0x0 0x8000>; +}; -- 2.34.1