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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3153dd9c96asm1643675eec.7.2026.07.30.22.53.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 22:53:50 -0700 (PDT) From: Dongfang Zhao Date: Thu, 30 Jul 2026 22:53:48 -0700 Subject: [PATCH v2 1/2] dt-bindings: clock: qcom: Add Hawi GPU clock controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260730-gpucc-hawi-v2-1-7bf618ab8a34@oss.qualcomm.com> References: <20260730-gpucc-hawi-v2-0-7bf618ab8a34@oss.qualcomm.com> In-Reply-To: <20260730-gpucc-hawi-v2-0-7bf618ab8a34@oss.qualcomm.com> To: mturquette@baylibre.com, robh@kernel.org, andersson@kernel.org, conor+dt@kernel.org, sboyd@kernel.org, krzk+dt@kernel.org Cc: linux-kernel@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, taniya.das@oss.qualcomm.com, bmasney@redhat.com X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785477228; l=6690; i=dongfang.zhao@oss.qualcomm.com; s=20260706; h=from:subject:message-id; bh=TbWn2omPVPJIUFrb413uT0CtEMn7ALcSOCfFDea8q0o=; b=Lpr4jff/WunGOZzFx51LAO2b7vBuX/mRxMATPtmKcSQw8y0hQsi014jobANWP5t3BXl4rSpLf 5Tjja03Y1yvB12BjBvWPsasxG+py0F+2kD1Obe+0s05xenvIizYm26t X-Developer-Key: i=dongfang.zhao@oss.qualcomm.com; a=ed25519; pk=oRbMthG8BHvTvcxks87U5rUBoZiRXWKs6KZR6lV5C64= X-Authority-Analysis: v=2.4 cv=ftzsol4f c=1 sm=1 tr=0 ts=6a6c386f cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=A1q_97lxy2FG9aqMPMkA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMxMDAzOCBTYWx0ZWRfX/Je03TqECLkY 9sxbMCpSQ4MELg4UrH8HcrbRDyeXLvGCC264+iJs719oVVCpuL9CZQm3qX/1mGczVx4NX8uUXcA gC7pCiNHzSmZTpFjbnNtIgEQ3jGhdgE= X-Proofpoint-ORIG-GUID: jBX2Z9JzmJV_wNryWFDqHM0p6g4piOtQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMxMDAzOCBTYWx0ZWRfXwJJSVYMPV9Xr aNgdqeRtsATpFIuyI3PQphQuwLFdbi6TvZOO0o/3tiQvPjFXeTcKfyL7QJvH0R9AZslcvgb3yXm phTWGSvnpu2wqAuuKb1ph++G/YCJggh84tbY9zkSOpPEj3+ZQzQsmGbT6iZiKE4pKZXM+cosi0+ 87nT++auwusoeBRdHTOQvD0zxo2Sx13m+wJUyeRdkLvpzVJv8XvMD4lbDc4SRUyqXLinbKdTcxQ yUMH11OK37A8xfRYm5/hulJB5UpmPzEr6LijMLV3VTv1b6eMpZuQAUQlTQ6XhXhRCd9X9vtOj4C tMqEWQaXQ+rt0a9yDjVfklBHBiChoBG0N2yYNeYii4HF8ogHWh3sVKsQehaWNlwvm+7JCzsVTd0 BZQrPzyQV5PcjJMwH9NsgoSNbBE5Ig3hGTnH4121rO/XstSLyMAMvgjS8wfi5LoX04UxriKpuCJ DF57px/meI+MVwoe3pQ== X-Proofpoint-GUID: jBX2Z9JzmJV_wNryWFDqHM0p6g4piOtQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-31_02,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 bulkscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607310038 Add the device tree binding and clock, reset and power-domain IDs for the Hawi graphics clock controller. This lets Hawi device trees describe the GPU clocks, resets and power domains, and lets dtbs_check validate those nodes. Add the qcom,hawi-gxclkctl compatible for the Hawi GX clock controller, using qcom,kaanapali-gxclkctl as the fallback because the register layout is identical. Signed-off-by: Dongfang Zhao --- .../devicetree/bindings/clock/qcom,hawi-gpucc.yaml | 78 ++++++++++++++++++++++ .../bindings/clock/qcom,kaanapali-gxclkctl.yaml | 22 +++--- include/dt-bindings/clock/qcom,hawi-gpucc.h | 47 +++++++++++++ 3 files changed, 139 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,hawi-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,hawi-gpucc.yaml new file mode 100644 index 000000000000..3e40bc3c061d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,hawi-gpucc.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,hawi-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on Hawi + +maintainers: + - Dongfang Zhao + +description: | + Qualcomm graphics clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also: include/dt-bindings/clock/qcom,hawi-gpucc.h + +properties: + compatible: + const: qcom,hawi-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + power-domains: + items: + - description: A phandle to the MX power-domain + - description: A phandle to the CX power-domain + - description: A phandle to the GMXC power-domain + + required-opps: + items: + - description: MX performance points + - description: CX performance points + - description: GMXC performance points + +required: + - compatible + - clocks + - power-domains + - required-opps + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,hawi-gpucc"; + reg = <0x0 0x03d90000 0x0 0x9800>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_GMXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs_d3>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml index e868963f659b..28b653f6b64d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml @@ -4,25 +4,31 @@ $id: http://devicetree.org/schemas/clock/qcom,kaanapali-gxclkctl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Graphics power domain Controller on Kaanapali +title: Qualcomm Graphics GX Power Domain Controller maintainers: - Taniya Das description: | - Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and - Power domains (GDSC). This module provides the power domains control - of gxclkctl on Qualcomm SoCs which helps the recovery of Graphics subsystem. + The Qualcomm graphics GX clock controller (GXCLKCTL) contains PLLs, clocks + and power domains (GDSC). This module provides the power domain control of + GXCLKCTL on Qualcomm SoCs, which helps the recovery of the graphics + subsystem. See also: include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h properties: compatible: - enum: - - qcom,glymur-gxclkctl - - qcom,kaanapali-gxclkctl - - qcom,sm8750-gxclkctl + oneOf: + - enum: + - qcom,glymur-gxclkctl + - qcom,kaanapali-gxclkctl + - qcom,sm8750-gxclkctl + - items: + - enum: + - qcom,hawi-gxclkctl + - const: qcom,kaanapali-gxclkctl power-domains: description: diff --git a/include/dt-bindings/clock/qcom,hawi-gpucc.h b/include/dt-bindings/clock/qcom,hawi-gpucc.h new file mode 100644 index 000000000000..181534771b10 --- /dev/null +++ b/include/dt-bindings/clock/qcom,hawi-gpucc.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_HAWI_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_HAWI_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CX_ACCU_SHIFT_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CXO_AON_CLK 4 +#define GPU_CC_CXO_CLK 5 +#define GPU_CC_DEMET_CLK 6 +#define GPU_CC_DPM_CLK 7 +#define GPU_CC_FREQ_MEASURE_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_GPU_SMMU_VOTE_CLK 10 +#define GPU_CC_GX_ACCU_SHIFT_CLK 11 +#define GPU_CC_HUB_AON_CLK 12 +#define GPU_CC_HUB_CLK_SRC 13 +#define GPU_CC_HUB_CX_INT_CLK 14 +#define GPU_CC_HUB_DIV_CLK_SRC 15 +#define GPU_CC_MEMNOC_GFX_CLK 16 +#define GPU_CC_MXG_AHB_CLK 17 +#define GPU_CC_MXG_XO_CLK 18 +#define GPU_CC_PLL0 19 +#define GPU_CC_RSCC_HUB_AON_CLK 20 +#define GPU_CC_RSCC_XO_AON_CLK 21 +#define GPU_CC_SLEEP_CLK 22 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_MXG_GDSC 1 + +/* GPU_CC resets */ +#define GPU_CC_CB_BCR 0 +#define GPU_CC_CX_BCR 1 +#define GPU_CC_FAST_HUB_BCR 2 +#define GPU_CC_GMU_BCR 3 +#define GPU_CC_GX_BCR 4 +#define GPU_CC_MXG_BCR 5 +#define GPU_CC_XO_BCR 6 + +#endif -- 2.43.0