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From: Laura Nao <laura.nao@collabora.com>
To: work@onurozkan.dev
Cc: a.hindborg@kernel.org, acourbot@nvidia.com, airlied@gmail.com,
	aliceryhl@google.com, bjorn3_gh@protonmail.com, boqun@kernel.org,
	dakr@kernel.org, daniel.almeida@collabora.com,
	deborah.brouwer@collabora.com, dri-devel@lists.freedesktop.org,
	gary@garyguo.net, kernel@collabora.com, laura.nao@collabora.com,
	linux-kernel@vger.kernel.org, lossin@kernel.org,
	ojeda@kernel.org, rust-for-linux@vger.kernel.org,
	simona@ffwll.ch, tamird@kernel.org, tmgross@umich.edu
Subject: Re: [PATCH v2] drm/tyr: add Job IRQ handling
Date: Thu, 30 Jul 2026 11:45:25 +0200	[thread overview]
Message-ID: <20260730094525.245487-1-laura.nao@collabora.com> (raw)
In-Reply-To: <20260729165121.768013-1-work@onurozkan.dev>

Hi Onur,

On 7/29/26 18:51, Onur Özkan wrote:
> On Wed, 29 Jul 2026 11:58:29 +0200
> Laura Nao <laura.nao@collabora.com> wrote:
>
>> +
>> +    fn handle(&self, status: u32) {
>> +        if JOB_IRQ_RAWSTAT::from_raw(status).glb() {
>> +            self.fw_ready.store(true, Ordering::Release);
>> +            self.job_irq_wait.wake_up_all();
>> +        }
>
> You enable both GLB and CSG above but only handle GLB, is this intentional? This
> means CSG will trigger the handler, do nothing and just get cleared, or am I
> missing something?
>

The series that will later add CSF interface support will likely only 
include a firmware readiness check at first, with CSG bit handling 
added at a later stage. That's why we're only handling the GLB bit for 
now, but I agree unmasking the CSG bits here is premature then. I can 
drop this in the next revision, keep only the GLB bit unmasking/handling 
and add a TODO comment for the CSG bits.

Thanks!

Laura


      reply	other threads:[~2026-07-30  9:45 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-29  9:58 Laura Nao
2026-07-29 12:12 ` Ewan Chorynski
2026-07-29 13:25   ` Laura Nao
2026-07-29 16:51 ` Onur Özkan
2026-07-30  9:45   ` Laura Nao [this message]

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